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LMK04832MPAPSEP Datasheet(PDF) 21 Page - Texas Instruments |
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LMK04832MPAPSEP Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 102 page  8.2 Functional Block Diagram Figure 8-1 shows the high level block diagram. CPOUT1 Internal Dual Core VCO Partially Integrated Loop Filter PLL2 _REF _2X_EN OSCIN_P OSCIN_N FB_ MUX 2X Control Registers STATUS_LD2 Device Control Input clock switching and Holdover CLKIN0_P CLKIN0_N CLKOUT6 CLKOUT8 SYSREF Div Switchable CLKIN0/1/2 R Divider (1 to 16,383) N1 Divider (1 to 16,383) R2 Divider (1 to 4,095) PLL 1 Phase Detector/ Charge Pump PLL2 Phase Detector/ Charge Pump N2 Divider (1 to 262,143) Clock Distribution Path N2 Prescaler (2 to 8) OSCOUT_P/CLKIN2_P CLKIN1_P/FIN_P/FBCLKIN_P PLL1 _NCLK _MUX PLL2 _NCLK _MUX SYNC STATUS_LD1 RESET/GPO CLKIN_SEL0 CLKIN_SEL1 Fin1 SCK SDIO CS# SPI CLKin MUX Fin1 CLKin0 _OUT _MUX CLKin0 CLKin0 FB Mux VCO_ MUX ÷ 2 FIN0_P FIN0_N CLKin1 _OUT _MUX Divider (8 to 8191) Pulser CLKOUT13_N CLKOUT13_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay CLKOUT0_N CLKOUT0_P CLKOUT1_N CLKOUT1_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay CLKOUT2_N CLKOUT2_P CLKOUT3_N CLKOUT3_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay CLKOUT4_N CLKOUT4_P CLKOUT5_N CLKOUT5_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay D SYSREF/SYNC Distribution Path SYSREF/SYNC Control CLKIN1_N/FIN_N/FBCLKIN_N OSCOUT_N/CLKIN2_N MUX Switching Control D MUX VCO0 VCO1 CLKOUT12_N CLKOUT12_P CLKOUT11_N CLKOUT11_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay CLKOUT10_N CLKOUT10_P CLKOUT9_N CLKOUT9_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay CLKOUT8_N CLKOUT8_P CLKOUT7_N CLKOUT7_P Div (1 to 1023) Dig. Delay A. Delay Dig. Delay CLKOUT6_N CLKOUT6_P Figure 8-1. High Level Block Diagram www.ti.com LMK04832-SEP SNAS838A – OCTOBER 2022 – REVISED NOVEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: LMK04832-SEP |
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