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LSF0108 Datasheet(PDF) 10 Page - Texas Instruments |
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LSF0108 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 31 page ![]() 8.3 Feature Description 8.3.1 Auto Bidirectional Voltage Translation All devices in the LSF family are auto bidirectional voltage level translators that are operational from 0.95 V to 4.5 V on the Vref_A supply and from 1.8 V to 5.5 V on the Vref_B supply. This allows bidirectional voltage translation between 0.95 V and 5.5 V without the need for a direction pin in open-drain or push-pull applications. The LSF family supports level translation applications with transmission speeds greater than 100 Mbps for open-drain systems using a 30-pF capacitance and 250-Ω pullup resistor. Both the output driver of the controller and the peripheral device output can be push-pull or open-drain (pull-up resistors may be required). During operation of the device, the B-side is often referred to as the high side while the A-side is referred to as the low side. 8.3.2 Output Enable To enable the I/O pins, the EN input should be tied directly to Vref_B during operation and both pins must be pulled up to the HIGH side (Vpu or VCCB) through a pull-up resistor (typically 200 kΩ). To ensure the high impedance state during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin should always be tied directly to the Vref_B pin and is recommended to be disabled by an open-drain driver without a pullup resistor. This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B is recommended for a stable supply at the device. 1.8 V Vref_A VCCB EN 200 k Vref_B 3.3 V A1 B1 0.1 F Figure 8-1. EN Pin Tied to Vref_B Directly and to VCCB Through a Pull-Up Resistor The supply voltage of open drain I/O devices can be completely different from the supplies used for the LSF and has no impact on the operation. For additional details on how to use the enable pin, see the Using the Enable Pin with the LSF Family video. Table 8-1. EN Pin Function Table INPUT EN(1) PIN Data Port State Tied directly to Vref_B An = Bn L Hi-Z (1) EN is controlled by Vref_B logic levels. LSF0108-Q1 SDLS967E – MAY 2016 – REVISED NOVEMBER 2022 www.ti.com 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: LSF0108-Q1 |
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