10 Layout

10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.

– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,

resulting in early system failures.

– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away

from the protected traces which are between the TVS and the connector.

• Route the protected traces as straight as possible.

• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible.

– Electric fields tend to build up on corners, increasing EMI coupling.

• If pin 1 or 2 is connected to ground, use a thick and short trace for this return path.

10.2 Layout Example

ESD751

ESD761

ESD761

Pin to GND

Legend

GND

VBUS

To power supply

CC2

CC1

ESD751

ESD751

SBU2

SBU1

ESD751

D-

D+

Figure 10-1. Layout Recommendation

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ESD751, ESD761

SLVSH10C – NOVEMBER 2022 – REVISED DECEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

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Product Folder Links: ESD751 ESD761