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FXPS7115D4 Datasheet(PDF) 42 Page - NXP Semiconductors |
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FXPS7115D4 Datasheet(HTML) 42 Page - NXP Semiconductors |
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42 / 75 page ![]() NXP Semiconductors FXPS7115D4 Digital absolute pressure sensor, 40 kPa to 115 kPa 7.7.11.2 DSP_CFG_U1 - DSP user configuration #1 register (address 40h) The DSP user configuration register #1 is a user programmable read/write register that contains DSP-specific configuration information. This register is included in the read/write array error detection. Changes to this register reset the DSP data path. The contents of the SNSDATA_x registers are not guaranteed until the DSP has completed initialization as specified in Table 105. Reads of the SNSDATA_x registers and sensor data requests should be prevented during this time. Bit 7 6 5 4 3 2 1 0 Symbol LPF[3:0] reserved reserved reserved reserved Factory default 0 0 1 1 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 64. DSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation LPF[3] LPF[2] LPF[1] LPF[0] Low Pass Filter Type 0 0 1 0 800 Hz, 4-Pole 0 0 1 1 1000 Hz, 4-Pole[1][2] Table 65. Low-pass filter selection bits (LPF[3:0]) [1] Default is 1000 Hz. [2] In case of POR, filter reverts to the default. Note: Using values other than those listed in Table 65 causes an error in the DEVSTAT. 7.7.11.3 DSP_CFG_U3 - DSP user configuration #3 register (address 42h) The DSP user configuration register #3 is a user programmable read/write register that contains DSP-specific configuration information. This register is included in the read/write array error detection. Changes to this register reset the DSP data path. The content of the SNSDATA_x registers are not guaranteed until the DSP has completed initialization. Reads of the SNSDATA_x registers and sensor data requests should be prevented during this time. This register is readable and writeable in SPI mode, and I2C mode. Bit 7 6 5 4 3 2 1 0 Symbol reserved DATATYPE0[1:0] reserved DATATYPE1[1:0] reserved reserved Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 66. DSP_CFG_U3 - DSP user configuration #3 register (address 42h) bit allocation 7.7.11.3.1 DSP data type 0 selection bits (DATATYPE0) The DSP data type 0 selection bits select the type of data to be included in the SNSDATA0_L and SNSDATA0_H registers. FXPS7115D4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved. Product data sheet Rev. 6 — 6 June 2022 42 / 75 |
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