LM7480 datasheet(29/44 Pages) TI

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10.3.2.1 Boost Converter components (C2, C3, L1)

Place a minimum of 1µF capacitor across drain of the FET to GND (C2) and across CAP pin of LM7472x-

Q1 to drain of the FET (C3). Use a 100µH inductor (L1) with saturation current rating >175mA. Example:

XPL2010-104ML from coil craft

10.3.2.2 Input and output capacitance

A minimum input capacitance CIN of 0.1 µF and output capacitance COUT of 0.1 µF is recommended.

10.3.2.3 VS Capacitance, Resistor and Zener Clamp

Minimum of 1-µF CVS capacitance is required. During 200-V load dump, resistor R1 and zener diode D1 are used

to protect VS pin from exceeding the maximum ratings by clamping VVS to 60 V. Choosing R1 = 10 kΩ, the peak

power dissipated in zener diode D1 = 60 V * (200 V - 60 V) / 10 kΩ = 0.840 W of peak power dissipation. SMA

package diode such as BZG03B62-M can handle 840mW peak power dissipation. Peak power dissipated in R1

= (200 V - 60 V)2 / 10 kΩ = 1.96 W. One 10-kΩ resistor in 1210 package with 0.5-W DC power rating and 200-V

rating can withstand 200 Load Dump for 350 ms.

10.3.2.4 Overvoltage Protection and Output Clamp

Resistors R2 and R3 connected in series is used to program the overvoltage threshold. Connecting R2 to VBATT

provides overvoltage cut-off and switching the connection to VOUT provides overvoltage clamp. The resistor

values required for setting the overvoltage threshold VOV to 37.0 V is calculated by solving Equation 7.

(8)

For minimizing the input current drawn from the battery through resistors R2 and R3, it recommended to use

higher value of resistance. Using high value resistors will add error in the calculations because the current

through the resistors at higher value will become comparable to the leakage current into the OV pin. Maximum

leakage current into the OV pin is 1 µA and choosing (R2 + R3) < 120 kΩ ensures current through resistors is

100 times greater than leakage through OV pin.

Based on the device electrical characteristics, VOVR is 1.233V V. To limit (R2 + R3) < 120 kΩ, select (R2) = 100

kΩ. Solving Equation 7 gives R3 = 3.45 kΩ.

Closest standard 1% resistor values are R2 = 100 kΩ and R3 = 3.48 kΩ.

10.3.2.5 MOSFET Q1 Selection

The VDS rating of the MOSFET Q1 should be minimum 200 V for a output cutoff design where output can reach

0 V while the load dump transient is present and should be a minimum of 164.5 V when output is clamped to 37

V (±1.5 V). The VGS rating is based on HGATE-OUT maximum voltage of 15 V. A 20-V VGS rated MOSFET is

recommended.

Power dissipation on MOSFET Q1 on a design where output is clamped is critical and SOA characteristics of the

MOSFET need to be considered with sufficient design margin for reliable operation.

10.3.2.6 Input TVS Selection

Two TVS diodes D3 and D4 are required at the input. The breakdown voltage of TVS in the positive side

should be higher than the maximum system voltage 200 V. On the negative side clamping, diode D4 is used to

clamp ISO 7637-2 pulse 1 and its selection is similar to procedure in TVS selection for 24-V Battery Systems.

SMBJ150A for D3 and SMBJ33CA for D4 are recommended.

10.3.2.7 MOSFET Q2 Selection

Design requirements for selecting Q2 is similar to MOSFET Q1 selection in Table 10-1 and hence the procedure

for selecting MOSFET Q2 is same as outlined in MOSFET Selection: Blocking MOSFET Q1. MOSFET

BUK7Y4R8-60E is selected based on the design requirements.

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LM7480

SNOSDD8 – DECEMBER 2022

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