Copyright

© ANPEC Electronics Corp.

Rev. A.4 - Jun., 2005

APW7066

www.anpec.com.tw

2

General Description (Cont.)

Ordering and Marking Information

Pin Description

1

3

2

4

6

5

7

9

8

10

12

11

FB1

COMP1

REFIN

FB2

COMP2

SS1/EN1

REFOUT

SS3/EN3

SS2/EN2

DRIVE3

VREF

FB3

24

22

23

21

19

20

18

16

17

15

13

14

VCC

BOOT1

LGATE1

VCC12

UGATE1

PGND

LGATE2

BOOT2

UGATE2

PGOOD

GND

FS/SYNC

TSSOP-24

TOP VIEW

GND

BOTTOM

SIDE

PAD

APW7066

Handling Code

Temp. Range

Package Code

Package Code

R : TSSOP-P *

QA : QFN-32

Operating Ambient Temp. Range

C : 0 to 70 C

Handling Code

TU : Tube

TR : Tape & Reel

TY : Tray (for QFN only)

Lead Free Code

L : Lead Free Device

Blank : Original Device

°

A PW7066 R :

A PW7066

XXXXX

XXXXX - Date Code

Lead Free Code

A PW7066 QA :

A PW7066

XXXXX

XXXXX - Date Code

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate

termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering

operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C

for MSL classification at lead-free peak reflow temperature.

32 LD 5x5 QFN32

Top View

REFIN

NC

REFOUT

SS1/EN1

1

8

16

9

SS3/EN3

DRIVE3

GND

BOTTOM

SIDE PAD

17

24

25

SS2/EN2

PGND_1

VCC12_1

LGATE1

PGND_2

NC

LGATE2

32

VCC12_2

VREF

UGATE1

the external clock. The possible synchronous frequency

is from 150kHz to 800kHz. There is no Rds(on)

sensing or under-voltage sensing on APW7066.

However, it provides a simple short-circuit protection

by monitoring theCOMP1 andCOMP2 for over-voltage.

When any of two pins exceeds their trip point and the

condition persists for 1-2 internal clock cycle (3-6us

at 300kHz), then it will shut down all regulators.