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APW7068 Datasheet(PDF) 13 Page - Anpec Electronics Coropration

Part # APW7068
Description  Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage
PDF  26 Pages
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Manufacturer  ANPEC [Anpec Electronics Coropration]
Direct Link  http://www.anpec.com.tw
Logo ANPEC - Anpec Electronics Coropration

APW7068 Datasheet(HTML) 13 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.2 - Jun., 2006
APW7068
www.anpec.com.tw
13
Function Descriptions
Power On Reset (POR)
The Power-On Reset (POR) function of APW7068
continually monitors the input supply voltage (VCC12),
ensures the supply voltage exceed its rising POR
threshold voltage. The POR function initiates soft-start
interval operation while VCC12 voltages exceed their
POR threshold and inhibits operation under disabled
status.
Soft-Start
Figure 1. shows the soft-start interval. When VCC12
reaches the rising POR threshold voltage, the internal
reference voltage is controlled to follow a voltage pro-
portional to the soft-start voltage. The soft-start inter-
val is variable by the oscillator frequency. The formu-
lation is given by:
Figure 2. shows more detail of the FB and FBL voltage
ramps. The FB and FBL voltage soft-start ramps are
formed with many small steps of voltage. The voltage
of one step is about 20mV in FB and FBL, and the
period of one step is about 64/FOSC. This method pro-
vides a controlled voltage rise and prevents the large
peak current to charge output capacitor. The FB volt-
age compares the FBL voltage to shift to an earlier time
the establishment as Figure2. The voltage estabilishment
time difference for FB and FBL is variable by the
oscillator. The formulation is given by:
560
2
F
1
)
t
(t
T
OSC
1
2
SS
×
=
−
∆
=
Over-Current Protection
Connect a resistor (Rocset) from this pin to GND, an
internal 40uA current source will flow through this
resistor and create a voltage drop, which will be
compared with the voltage across the lower MOSFET.
When the voltage across the lower MOSFET exceeds
the voltage drop across the R
OCSET, an over-current
condition is detected and the controller will shut-
down the IC directly, and the converter's output is
latched.
Figure 2. The Controlled Stepped FB and FBL
Voltage during Soft-Start
SS
OSC
3
4
T
4
1
6
F
1
)
t
(t
×
=
×
=
−
∆
40
Figure 1. Soft-Start Interval
Voltage(V)
Time
FB
FBL
20mV
20mV
32/Fosc
32/Fosc
t 3
t 4
t 1
t 2
Voltage(V)
Time
VCC12
VOUT2
V
OUT1
t 0
POR



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