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FT800 Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000039 Clearance No.: BRT#001

4.8.3

Power Modes

When supply to VCCIO and VCC is applied, internal 1.2V regulator is powered by VCC. An internal POR

pulse will be generated during the regulator power up until it is stable. After the initial power up, the

FT800 will stay in STANDBY state. When needed, host can set FT800 to ACTIVE state by performing a

dummy read to address 0. The graphics engine, the audio engine and the touch engine are only

functional in ACTIVE state. To save power host can send command to put FT800 into any of the low

power mode: STANDBY, SLEEP and POWERDOWN. In addition, host is allowed to put FT800 in

POWERDOWN mode by drive PD_N pin to low, regardless what current state it is in. Refer to Figure 4-9

Power State Transition for the power state transitions.

Figure 4-9 Power State Transition

4.8.3.1 ACTIVE state

In ACTIVE state, the FT800 is in normal operation. The crystal oscillator and PLL are functioning. The

system clock applied to the FT800 core engines is enabled.

4.8.3.2 STANDBY state

In STANDBY state, the crystal oscillator and PLL remain functioning; the system clock applied to the

FT800 core engines is disabled. All register contents are retained.

4.8.3.3 SLEEP state

In SLEEP state, the crystal oscillator, PLL and system clock applied to the FT800 core engines are

disabled. All register contents are retained.

4.8.3.4 POWERDOWN state

In POWERDOWN state, the internal 1.2V regulator supplying the core digital logic, the crystal oscillator,

the PLL and the system clock applied to the FT800 core is disabled. All register contents are lost and

reset to default when the chip is next switched on.

POWERDOWN

STANDBY

SLEEP

VCC/VCCIO

Power ON

Toggle PD_N from high

to low

ACTIVE

Toggle PD_N from low

to high

Toggle PD_N from high

to low

Toggle PD_N from high to low or

Write command “POWERDOWN”

Write command “SLEEP”

Write command

“STANDBY”

Dummy Read “0”

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