FT800Q-R datasheet(13/46 Pages) BRIDGETEK

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FT800 Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000039 Clearance No.: BRT#001

For I2C memory read transaction, bytes are packed in the I2C protocol as follow:

[start] <DEVICE ADDRESS + write bit>

<00b+Address[21:16]>

<Address[15:8]>

<Address[7:0]>

[restart] <DEVICE ADDRESS + read bit>

....

<Read data byte n>[stop]

4.1.5

Host Memory Write

For SPI memory write transaction, the host sends a ‘1’ bit and ‘0’ bit, followed by the 22-bit address. This

is followed by the write data.

Byte n

Table 4-2 Host memory write transaction (SPI)

For I2C, memory write transaction bytes are packed in the I2C protocol as follow:-

[start] <DEVICE ADDRESS + write bit>

<10b,Address[21:16]>

<Address[15:8]>

<Address[7:0]>

....

<Write data byte n> [stop]

4.1.6

Host Command

When sending a command, the host transmits a 3 byte command. Table 4-3 lists all the host command

functions.

Note: ACTIVE command is generated by dummy memory read from address 0 when FT800 is in sleep or

standby mode.

For SPI command transaction, the host sends a ‘0’ bit and ‘1’ bit, followed by the 6-bit command code.

This is followed by 2 bytes 00h.

Table 4-3 Host command transaction (SPI)

Address [21:16]

Address [15:8]

Address [7:0]

Byte 0

Command [5:0]

Write Data

Write

Address

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