FT800Q-R datasheet(12/46 Pages) BRIDGETEK

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FT800 Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000039 Clearance No.: BRT#001

4.1.1

SPI Interface

The SPI slave interface operates up to 30MHz. Only SPI mode 0 is supported. Refer to section 6.4.2 for

detailed timing specification.

The SPI interface is selected when the MODE pin is tied to GND.

4.1.2

I²C Interface

The I²C slave interface operates up to 3.4MHz, supporting standard-mode, fast-mode, fast-mode plus

and high-speed mode. Refer to section 6.4.3for detailed timing specification.

The I²C device address is configurable between 20h to 27h depending on the I²C_SA[2:0] pin setting,

i.e. the 7-bit I2C slave address is 0b’0100A2A1A0.

The I²C interface is selected when the MODE pin is tied to VCCIO.

4.1.3

Serial Data Protocol

The FT800 appears to the host MPU/MCU as a memory-mapped SPI or I²C device. The host

communicates with the FT800 using reads and writes to a large (4 megabyte) address space. Within this

address space are dedicated areas for graphics, audio and touch control. Refer to section 5 for the

detailed memory map.

The host reads and writes the FT800 address space using SPI or I²C transactions. These transactions are

memory read, memory write and command write. Serial data is sent by the most significant bit first. For

I²C transactions, the same byte sequence is encapsulated in the I²C protocol.

For SPI operation, each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s

no limit on data length within one transaction, as long as the memory address is continuous.

4.1.4

Host Memory Read

For SPI memory read transaction, the host sends two zero bits, followed by the 22-bit address. This is

followed by a dummy byte. After the dummy byte, the FT800 responds to each host byte with read data

bytes.

Byte n

Table 4-1 Host memory read transaction (SPI)

Address [21:16]

Address [15:8]

Address [7:0]

Dummy byte

Byte 0

Read Data

Write

Address

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