SST26WF040BA datasheet(22/96 Pages) MICROCHIP

22 / 96 page

SST26WF040B/040BA SST26WF080B/080BA

DS20005283C-page 22

 2014-2017 Microchip Technology Inc.

5.12

SPI Dual-Output Read

The SPI Dual-Output Read instruction supports up to

104 MHz frequency. Initiate SPI Dual-Output Read by

executing an 8-bit command, 3BH, followed by address

bits A[23-0] and a dummy byte. CE# must remain

active low for the duration of the SPI Dual-Output Read

operation. See Figure 5-13 for the SPI Quad Output

Read sequence.

Following the dummy byte, the SST26WF040B/040BA

and SST26WF080B/080BA output data from SIO[1:0]

starting from the specified address location. The device

continually streams data output through all addresses

until terminated by a low-to-high transition on CE#. The

internal address pointer automatically increments until

the highest memory address is reached, at which point

the address pointer returns to the beginning of the

address space.

FIGURE 5-13:

FAST READ, DUAL-OUTPUT SEQUENCE

5.13

SPI Dual I/O Read

The SPI Dual I/O Read (SDIOR) instruction supports

up to 80 MHz frequency. Initiate SDIOR by executing

an 8-bit command, BBH. The device then switches to

2-bit I/O mode for address bits A[23-0], followed by the

Set Mode configuration bits M[7:0]. CE# must remain

active low for the duration of the SPI Dual I/O Read.

See Figure 5-14 for the SPI Dual I/O Read sequence.

Following the Set Mode configuration bits, the

SST26WF040B/040BA and SST26WF080B/080BA

outputs data from the specified address location. The

device continually streams data output through all

addresses until terminated by a low-to-high transition

on CE#. The internal address pointer automatically

increments until the highest memory address is

reached, at which point the address pointer returns to

the beginning of the address space.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SPI Dual I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another SDIOR com-

mand, BBH, and does not require the op-code to be

entered again. The host may set the next SDIOR cycle

by driving CE# low, then sending the two-bit wide input

for address A[23:0], followed by the Set Mode configu-

ration bits M[7:0]. After the Set Mode configuration bits,

the device outputs the data starting from the specified

address location. There are no restrictions on address

location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. See Fig-

ure 5-15 for the SPI Dual I/O Read sequence when

M[7:0] = AXH.

CE#

SIO0

SCK

012345678

31 32

MODE 3

MODE 0

15 16

3BH

20005283 F52.3

39 40 41

A[23:16]

A[15:8]

A[7:0]

b6 b5

SIO1

Address

OP Code

Data

Byte 0

Dummy

Data

Byte N

b3 b1

b7 b4

b2 b0

MSB

Note: MSB = Most Significant Bit.

SST26WF040BA Datasheet(PDF) 22 Page - Microchip Technology

SST26WF040BA Datasheet(HTML) 22 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL