SST26WF040BA datasheet(33/96 Pages) MICROCHIP

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 2014-2017 Microchip Technology Inc.

DS20005283C-page 33

SST26WF040B/040BA SST26WF080B/080BA

5.31

Write-Enable (WREN)

The Write Enable (WREN) instruction sets the Write-

Enable-Latch bit in the Status register to ‘1,’ allowing

Write operations to occur. The WREN instruction must

be executed prior to any of the following operations:

Sector Erase, Block Erase, Chip Erase, Page Program,

Program Security ID, Lockout Security ID, Write Block-

Protection Register, Lock-Down Block-Protection Reg-

ister, and Non-Volatile Write-Lock Lock-Down Register,

SPI Quad Page Program, and Write Status Register. To

execute a Write Enable the host drives CE# low then

sends the Write Enable command cycle (06H) then

drives CE# high. See Figures 5-32 and 5-33 for the

WREN instruction sequence. See Figures 5-32 and 5-

33 for the WREN instruction sequence.

FIGURE 5-32:

WRITE-ENABLE

SEQUENCE (SQI)

FIGURE 5-33:

WRITE-ENABLE

SEQUENCE (SPI)

5.32

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction sets the Write-

Enable-Latch bit in the Status register to ‘0,’ preventing

Write operations. The WRDI instruction is ignored

during any internal write operations. Any Write opera-

tion started before executing WRDI will complete. Drive

CE# high before executing WRDI.

To execute a Write-Disable, the host drives CE# low,

sends the Write Disable command cycle (04H), then

drives CE# high. See Figures 5-34 and 5-35.

FIGURE 5-34:

WRITE-DISABLE (WRDI)

SEQUENCE (SQI)

FIGURE 5-35:

WRITE-DISABLE (WRDI)

SEQUENCE (SPI)

20005283 F12.1

MODE 3

SCK

SIO[3:0]

CE#

MODE 0

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

20005283 F18.0

MSB

20005283 F33.1

MODE 3

SCK

SIO(3:0)

CE#

MODE 0

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

20005283 F19.0

MSB

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