ADM487EARZ datasheet(4/16 Pages) AD

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ADM485E/ADM487E/ADM1487E

Rev. B | Page 4 of 16

TIMING SPECIFICATIONS

VCC = 5 V ± 10%, TA = TMIN to TMAX, unless otherwise noted.

Table 3. ADM485E/ADM1487E

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

DRIVER

Driver Propagation Delay Input to Output, Low to High

tDPLH

RDIFF = 54 Ω, CL1 = CL2 = 100 pF

(see

Figure 19 and Figure 20)

Driver Propagation Delay Input to Output, High to Low

tDPHL

RDIFF = 54 Ω, CL1 = CL2 = 100 pF

(see

Figure 19 and Figure 20)

Output Skew to Output

tSKEW

RDIFF = 54 Ω, CL1 = CL2 = 100 pF

(see

Figure 19 and Figure 20)

Rise/Fall Time

tDR, tDF

RDIFF = 54 Ω, CL1 = CL2 = 100 pF

(see

Figure 19 and Figure 20)

Enable Time to High Level

tDZH

CL = 100 pF, S1 closed (see

Figure 21)

Enable Time to Low Level

tDZL

CL = 100 pF, S1 closed (see

Figure 22)

Disable Time from Low Level

tDLZ

CL = 15 pF, S1 closed (see

Figure 22)

Disable Time from High Level

tDHZ

CL = 15 pF, S1 closed (see

Figure 21)

RECEIVER

Receiver Propagation Delay Input to Output, Low to High

tRPLH

200

See

Figure 23 and Figure 24

Receiver Propagation Delay Input to Output, High to Low

tRPHL

200

See

Figure 23 and Figure 24

|tPLH − tPHL| Differential Receiver Skew

tSKEW

See

Figure 23 and Figure 24

Enable Time to Low Level

tRZL

CL = 15 pF, S2 closed (see

Figure 25)

Enable Time to High Level

tRZH

CL = 15 pF, S1 closed (see

Figure 25)

Disable Time from Low Level

tRLZ

CL = 15 pF, S2 closed (see

Figure 25)

Disable Time from High Level

tRHZ

tPLH, tPHL < 50% of data period

MAXIMUM DATA RATE

fMAX

2.5

Mbps

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