ADF4219LBRU datasheet(19/24 Pages) AD

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REV. C

ADF4217L/ADF4218L/ADF4219L

–19–

PROGRAM MODES

Tables IV and VII show how to set up the program modes in the

ADF4217L family. The following should be noted:

1. IF and RF Analog Lock Detect indicate when the PLL is in

lock. When the loop is locked, and either IF or RF Analog

Lock Detect is selected, the MUXOUT pin will show a logic

high with narrow low-going pulses. When the IF/RF Analog

Lock Detect is chosen, the locked condition is indicated only

when both IF and RF loops are locked.

2. The IF Counter Reset Mode resets the R and N counters in

the IF section and also puts the IF charge pump into three-

state. The RF Counter Reset Mode resets the R and N counters

in the RF section and also puts the RF charge pump into

three-state. The IF and RF Counter Reset Mode does both

of the above.

Upon removal of the reset bits, the N counter resumes counting

in close alignment with the R counter (maximum error is one

prescaler output cycle).

3. The Fastlock Mode uses MUXOUT to switch a second loop

filter damping resistor to ground during Fastlock operation.

Activation of Fastlock occurs whenever RF CP Gain in the

RF Reference counter is set to 1.

POWER-DOWN

It is possible to program the ADF4217L family for either synchro-

nous or asynchronous power-down on either the IF or RF side.

Synchronous IF Power-Down

Programming a “1” to P7 of the ADF4217L family will initiate a

power-down. If P2 of the ADF4217L family has been set to “0”

(normal operation), then a synchronous power-down is conducted.

The device will automatically put the charge pump into three-

state and then complete the power-down.

Asynchronous IF Power-Down

If P2 of the ADF4217L family has been set to “1” (three-state the

IF charge pump) and P7 is subsequently set to “1,” an asynchro-

nous power-down is conducted. The device will go into power-down

on the rising edge of LE, which latches the “1” to the IF Power-

Down Bit (P7).

Synchronous RF Power-Down

Programming a “1” to P16 of the ADF4217L family will initiate a

power-down. If P10 of the ADF4217L family has been set to “0”

(normal operation), a synchronous power-down is conducted. The

device will automatically put the charge pump into three-state

and then complete the power-down.

Asynchronous RF Power-Down

If P10 of the ADF4217L family has been set to “1” (three-state

the RF charge pump) and P16 is subsequently set to “1,” an

asynchronous power-down is conducted. The device will go into

power-down on the rising edge of LE, which latches the “1” to

the RF Power-Down Bit (P16).

Activation of either synchronous or asynchronous power-down

forces the IF/RF loop’s R and N dividers to their load state

conditions, and the IF/RF input section is debiased to a high

impedance state.

The REFIN oscillator circuit is only disabled if both the IF and

RF power-downs are set.

The input register and latches remain active and are capable of

loading and latching data during all the power-down modes.

The IF/RF section of the devices will return to normal powered-up

operation immediately upon LE latching a “0” to the appropriate

power-down bit.

IF SECTION

Programmable IF Reference (R) Counter

If control bits C2, C1 are 0, 0, then the data is transferred from

the input shift register to the 14-bit IF R counter. Table IV shows

the input shift register data format for the IF R counter and the

possible divide ratios.

IF Phase Detector Polarity

P1 sets the IF phase detector polarity. When the IF VCO char-

acteristics are positive, this should be set to “1.” When they are

negative, it should be set to “0.” See Table IV.

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when programmed

to a “1.” It should be set to “0” for normal operation. See Table IV.

IF Charge Pump Currents

P5 sets the IF charge pump current. With P5 set to “0,” ICP is

1.0 mA. With P5 set to “1,” ICP is 4.0 mA. See Table IV.

Programmable IF AB Counter

If control bits C2, C1 are 0, 1, the data in the input register is

used to program the IF AB counter. For the ADF4217L/ADF4218L,

the AB counter consists of a 6-bit swallow counter (A counter)

and 11-bit programmable counter (B counter). Table V shows

the input register data format for programming the IF AB counter

and the possible divide ratios. The ADF4219L N counter consists

of an 13-bit B counter and 5-bit A counter. Table VI shows the

input register data format for programming the ADF4219L.

IF Prescaler Value

P6 in the IF AB counter latch sets the IF prescaler value. For

the ADF4217L family, 8/9 or 16/17 prescalers are available. See

Table V and Table VI.

IF Power-Down

Tables IV, V, and VI show the power-down bits in the ADF4217L

family. See the Power-Down section for a functional description.

RF SECTION

Programmable RF Reference (R) Counter

If control bits C2, C1 are 1, 0, the data is transferred from the

input shift register to the 14-bit RF R counter. Table VII shows the

input shift register data format for the RF R counter and the

possible divide ratios.

RF Phase Detector Polarity

P9 sets the RF phase detector polarity. When the RF VCO

characteristics are positive, this should be set to “1.” When they

are negative, it should be set to “0.” See Table VII.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when programmed

to a “1.” It should be set to “0” for normal operation. See Table VII.

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