ADF4219LBRU datasheet(21/24 Pages) AD

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REV. C

ADF4217L/ADF4218L/ADF4219L

–21–

SPI COMPATIBLE SERIAL BUS

LOCK

DETECT

VCO190-1750T

VCC

CPIF

IFIN

REFIN

CLK

DATA

RFIN

MUXOUT

CPRF

VP1

VP2VDD2VDD1

ADF4217L/

ADF4218L/

ADF4219L

VCO190-200T

VCC

10MHz

TCXO

DECOUPLING CAPACITORS (22 F/10pF) ON VDD , VP OF THE ADF4217L/ADF4218L/ADF4219L.

THE TCXO AND ON VCC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

2.4pF

450pF

24nF

100pF

760pF

7.5nF

690pF

100pF

3.3k

1.5k

3.3k

RFOUT

VDD

IFOUT

4.7k

Figure 8. Local Oscillator Design for WCDMA System

In this circuit, the reference input signal is applied to the circuit

at REFIN by a 10 MHz TCXO (temperature controlled crystal

oscillator).

INTERFACING

The ADF4217L/ADF4218L/ADF4219L family has a simple

SPI

® compatible serial interface for writing to the device. SCLK,

SDATA, and LE control the data transfer. When LE (latch

enable) goes high, the 22 bits that have been clocked into the

input register on each rising edge of SCLK will get transferred

to the appropriate latch. See Figure 1 for the timing diagram

and Table I for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This means

that the maximum update rate possible for the device is 909 kHz

or one update every 1.1

µs. This is certainly more than adequate

for systems that will have typical lock times in hundreds of

microseconds.

ADuC812 Interface

Figure 9 shows the interface to the ADuC812 MicroConverter

®.

Since the ADuC812 is based on an 8051 core, this interface can

be used with any 8051 based microcontroller. The MicroConverter

is set up for SPI Master Mode with CPHA = 0. To initiate the

operation, the I/O port driving LE is brought low. Each latch of

the ADF421xL family needs a 22-bit word. This is accomplished

by writing three 8-bit bytes from the MicroConverter to the

device. When the third byte has been written, the LE input should

be brought high to complete the transfer.

On first applying power to the ADF4217L family, it needs four

writes (one each to the R counter latch and the AB counter latch

for both RF1 and RF2 side) for the output to become active.

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be about

180 kHz.

ADF4217L/

ADF4218L/

ADF4219L

CLK

DATA

MUXOUT

(LOCK DETECT)

ADuC812

SCLK

MOSI

I/O PORTS

Figure 9. ADuC812 to ADF421xL Interface

ADSP2181 Interface

Figure 10 shows the interface between the ADF4217L family and

the ADSP-21xx digital signal processor. As previously discussed,

the ADF4217L family needs a 22-bit serial word for each latch

write. The easiest way to accomplish this using the ADSP-21xx

family is to use the autobuffered transmit mode of operation

with alternate framing. This provides a means for transmitting

an entire block of serial data before an interrupt is generated.

Set up the word length for eight bits and use three memory loca-

tions for each 22-bit word. To program each 22-bit latch, store

the three 8-bit bytes, enable the Autobuffered Mode, and then

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

ADF4217L/

ADF4218L/

ADF4219L

CLK

DATA

MUXOUT

(LOCK DETECT)

ADSP-21xx

SCLK

TFS

I/O FLAG

Figure 10. ADSP-21xx to ADF421xL Interface

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