Philips Semiconductors

Product specification

74F173

Quad D-type flip–flop (3-State)

August 31, 1990

3

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

9

8

VCC

OE0

OE1

Q0

Q1

Q2

Q3

CP

GND

MR

D0

D3

D2

Q2

E1

E0

SF00290

LOGIC SYMBOL

Q0 Q1 Q2 Q3

VCC = Pin 16

GND = Pin 8

D0 D1 D2 D3

14 13 12 11

E0

E1

CP

MR

OE0

OE1

9

10

7

15

1

2

3456

SF00291

IEC/IEEE SYMBOL

14

13

12

11

&

9

10

7

1

2

15

1D

C1

&

R

3

4

5

6

EN

SF00292

FUNCTION TABLE

INPUTS

OUTPUTS

OUTPUTS

MR

CP

E0

E1

Dn

Qn (register)

H

X

X

X

X

L

Reset (clear)

L

↑

l

l

l

L

Parallel load

L

↑

l

l

h

H

L

X

h

X

X

qn

Hold (do nothing)

L

X

X

h

X

qn

Notes to function table

H = High–voltage level

h

= High state one setup time before the low–to–high clock transition

L

= Low–voltage level

l

= Low state one setup time before the low–to–high clock transition

qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low–to–high clock transition

X = Don’t care

↑ = Low–to–high clock transition