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AOZ1380DI Datasheet(PDF) 21 Page - Alpha & Omega Semiconductors |
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AOZ1380DI Datasheet(HTML) 21 Page - Alpha & Omega Semiconductors |
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21 / 24 page ![]() Rev. 1.3 December 2020 www.aosmd.com Page 21 of 24 AOZ1380DI ALPHA & OMEGA SEMIC ONDUCT OR drop. It is also to prevent high-frequency noise on the power line from passing through to the output. The V5V capacitor should be located as close to the pin as possible. A 20μF ceramic capacitor is recommended. However, higher capacitor values further reduce the transient voltage drop at the input. VCHG Capacitor Selection The VCHG capacitor for sinking path has to supply enough current for a large load that it may encounter during system transient. This bulk capacitor must be large enough to supply fast transient load in order to prevent the output from dropping. If VCHG capacitor is too large and the output voltage is lower than approximately 300mV of the input voltage at the end of soft-start-time, short-circuit protection will be triggered to turn-off the power switch. Layout Guidelines AOZ1380DI is a protection switch designed deliver high current. Layout is critical to remove the heat generated by this current. For the most efficient heat sinking, connect as much copper as possible to the exposed pad. The exposed pad is the common drain of the power switch which must be electrically isolated. On the top layer expand the exposed pad island as much as possible for optimal thermal performance. The exposed pad copper plane must be electrically isolated. See example in Figure 28. Figure 28. Top layer layout. Maximum number of VIAs from top layer exposed pad to inner layer. There are two ways to create thermal islands on the inner layers. If the layer is flooded with a plane an isolated pad may be etched out as showed in Figure 29. If there are no flooded planes then an isolated island may be created as showed in Figure 29. The more layers that have these electrically isolated thermal heat sink islands the better the thermal performance will be. Connect all isolated thermal island (top, inner layers and bottom) together with as many VIAs as possible. Figure 29. Inner layer layout. Create electrically isolated thermal island with flooded plane. Figure 30. Inner layer layout. Create an isolated island with no flooded plane. On the bottom layer, similar to the inner layers, create an isolated thermal island. Typically, there is more area available on the bottom area for a larger thermal pad. The top and bottom layers have better thermal performance than the inner layers because they are exposed to the atmosphere. See example in Figure 31. Figure 31. Bottom layer layout. Create a large electrically isolated thermal pad. |
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