QL4058 datasheet(13/23 Pages) ETC1

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QL4058 QuickRAM Data Sheet Rev H

JTAG

Figure 10: JTAG Block Diagram

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design

challenges. One of these challenges concerns the accessibility of test points. The Joint Test

Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard

1149.1, the Standard Test Access Port and Boundary Scan Architecture.

The JTAG boundary scan test methodology allows complete observation and control of the

boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port

(TAP) controller works in concert with the Instruction Register (IR); these allow users to run

three required tests, along with several user-defined tests.

JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse

subsystem tests for fuller verification of higher level system elements.

TCK

TMS

TRSTB

RDI

TDO

Instruction Decode

Control Logic

TAp Controller

State Machine

(16 States)

Instruction Register

Boundary-Scan Register

(Data Register)

Mux

Bypass

Mux

Internal

I/O Registers

User Defined Data Register

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