P9415-R datasheet(43/62 Pages) RENESAS

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P9415-R Datasheet

May 4, 2021

Address

and Bit

R/W

Default

Value

Function and Description

0x28 [3]

VSWITCHSUCCESS

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [2]

OVERTEMP

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [1]

OVERVOLT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [0]

OVERCURR

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

Note: The bit definition in Rx mode and Tx mode is different.

Table 22. System Interrupt Clear Register (0x28, 0x29, 0x2A, 0x2B) in Tx Mode

Address

and Bit

R/W

Default

Value

Function and Description

0x2B [7:0]

Reserved

R/W

Reserved

0x2A [7:0]

Reserved

R/W

Reserved

0x29 [7:1]

Reserved

R/W

Reserved

0x29 [0]

CSP_RECEIVE_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [7]

TX_INIT_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [6]

GET_DPING_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [5]

MODECHNGED

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [4]

GET_CFG_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [3]

GET_ID_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [2]

GET_SS_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [1]

START_DPING_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

0x28 [0]

EPT_TYPE_INT

R/W

AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared

to 0 (by M0) afterward.

Note: The bit definition in Rx mode and Tx mode is different.

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