P9415-R datasheet(57/62 Pages) RENESAS

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P9415-R Datasheet

May 4, 2021

Table 52. FOD High Segment Threshold Register in Tx Mode (0xAA)

Address

and Bit

R/W

Default

Value

Function and Description

0xAA [15:0]

fodThdH

R/W

0xFF9C FOD threshold for high level segment in Tx mode, value in mW.

Table 53. FOD Segment Threshold Register in Tx Mode (0xAC)

Address

and Bit

R/W

Default

Value

Function and Description

0xAC [15:0]

fodSegThd

R/W

0x0E74

Threshold for two segment FOD threshold. Value in mW.

If Rx Power is higher than FOD Segment Threshold, the High Level FOD Threshold

is used, otherwise, the Low Level FOD Threshold is used as FOD threshold.

Table 54. Ping Interval Register in Tx Mode (0xBA)

Address

and Bit

R/W

Default

Value

Function and Description

0xBA [15:0]

PingInterval

R/W

0x038E The interval between each digital ping, value in ms.

11.1Bi-di Communication Registers

Table 55. Write Data Type and Length Register for WPC 1.3 (0x1A0)

Address

and Bit

R/W

Default

Value

Function and Description

0x1A1[7]

WrLsSize

R/W

7 LSB of packet size

0x1A0[7:5]

WrMsSize

R/W

3 MSB of packet size

0x1A0 [4:0]

WrType

R/W

Type of packet

Table 56. Write Data Register for WPC 1.3 (0x1A4~0x39F)

Address

and Bit

R/W

Default

Value

Function and Description

0x1A4[508]

WrData

R/W

Raw data which is intended to send to Tx

Table 57. Read Data Register for WPC 1.3 (0x3A4~0x59F)

Address

and Bit

R/W

Default

Value

Function and Description

0x3A4[508]

RdData

Raw data which is received from Tx

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