 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
74F8962 Datasheet(PDF) 1 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
74F8962 Datasheet(HTML) 1 Page - NXP Semiconductors |
|
|
1 / 10 page  Philips Semiconductors FAST Products Product specification 74F8962/8963 9-Bit latched bidirectional Futurebus transceivers (open-collector) 1 March 11, 1993 853–1425 09230 FEATURES • Octal latched transceiver • Drives heavily loaded backplanes with equivalent load impedances down to 10 Ω • High drive (100mA) open collector drivers on B port • Reduced voltage swing (1 volt) produces less noise and reduces power consumption • High speed operation enhances performance of backplane buses and facilitates incident wave switching • Compatible with IEEE 896 futurebus standards • Built–in precision band–gap reference provides accurate receiver thresholds and improved noise immunity • Multiple GND pins minimize ground bounce • Glitch–free power up/power down operation DESCRIPTION The 74F8962 and 74F8963 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired-OR bus. The B port inverting drivers are low-capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 150mV threshold region. The B port interfaces to ‘Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching to 9 Ω is guaranteed. The voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8962 and 74F8963 A ports have TTL 3-state drivers and TTL receivers with a latch function. The 74F8963 is the non-inverting version of 74F8962. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL) 74F8962 6.5ns 90mA 74F8963 5.5ns 90mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 44–pin Quad Flat Pack1 N74F8962Y, N74F8963Y 44–pin Plastic Leaded Chip Carrier N74F8962A, N74F8963A Note to ordering information 1. Flatpack package is not available at this time. INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW AI0 – AI8 PNP latched inputs 1.0/0.167 20 µA/100µA B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100 µA/100µA OEAB, OEBA Output enable inputs (active low) 1.0/0.033 20 µA/20µA LEAB, LEBA Latch enable inputs (active low) 1.0/0.033 20 µA/20µA AO0 – AO8 3–state outputs 150/40 3mA/24mA B0 – B8 Open collector outputs OC/166.7 OC/100mA Notes to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20 µA in the high state and 0.6mA in the low state. 2. OC = Open collector. |
Similar Part No. - 74F8962 |
|
Similar Description - 74F8962 |
|
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
