12

Figure 11. Recommended Logic Interface.

Figure 12. Operating Circuit for Burn-In and

Steady State Life Tests. All Channels Tested

Simultaneously.

V FF

GND

V CM

R L

+5 V

V O

+

PULSE GEN.

NOTE: BASE LEAD NOT CONNECTED.

A

B

D.U.T.

SINGLE CHANNEL OR

-

Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.

GND

V CC

D.U.T.

R L

220

Ω

5 V

V CC

LOGIC GATE

0.01 µF

EACH CHANNEL

TTL

GND

D.U.T.*

NOTE: BASE LEAD NOT CONNECTED.

T A = +125 ˚C

NOMINAL CONDITIONS

+

(EACH OUTPUT)

(EACH INPUT)

0.1 µF

-

*The equivalent output load resistance is affected by the LSTTL input current and is

approximately 8.2 k

Ω. This is a worst case design which takes into account 25%

degradation of CTR. See App. Note 1002 to assess actual degradation and lifetime.

Logic Family

LSTTL

CMOS

Device No.

54LS14

CD40106BM

5 V

5 V

15 V

18 k

Ω *8.2 kΩ

22 k

Ω