ADC081000LEVAL datasheet(28/29 Pages) NSC

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Applications Information (Continued)

8.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are es-

sential to ensure accurate conversion. A single ground plane

should be used, as opposed to splitting the ground plane into

analog and digital areas.

Since digital switching transients are composed largely of

high frequency components, the skin effect tells us that total

ground plane copper weight will have little effect upon the

logic-generated noise. Total surface area is more important

than is total ground plane volume. Coupling between the

typically noisy digital circuitry and the sensitive analog cir-

cuitry can lead to poor performance that may seem impos-

sible to isolate and remedy. The solution is to keep the

analog circuitry well separated from the digital circuitry.

High power digital components should not be located on or

near any linear component or power supply trace or plane

that services analog or mixed signal components as the

resulting common return current path could cause fluctuation

in the analog input “ground” return of the ADC, causing

excessive noise in the conversion result.

Generally, we assume that analog and digital lines should

cross each other at 90˚ to avoid getting digital noise into the

analog path. In high frequency systems, however, avoid

crossing analog and digital lines altogether. Clock lines

should be isolated from ALL other lines, analog AND digital.

The generally accepted 90˚ crossing should be avoided as

even a little coupling can cause problems at high frequen-

cies. Best performance at high frequencies is obtained with a

straight signal path.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. This is

especially important with the low level drive required of the

ADC081000. Any external component (e.g., a filter capaci-

tor) connected between the converter’s input and ground

should be connected to a very clean point in the analog

ground plane. All analog circuitry (input amplifiers, filters,

etc.) should be separated from any digital components.

9.0 DYNAMIC PERFORMANCE

The ADC081000 is a.c. tested and its dynamic performance

is guaranteed. To meet the published specifications and

avoid jitter-induced noise, the clock source driving the CLK

input must exhibit low rms jitter. The allowable jitter is a

function of the input frequency and the input signal level, as

described in Section 4.0.

It is good practice to keep the ADC clock line as short as

possible, to keep it well away from any other signals and to

treat it as a transmission line. Other signals can introduce

jitter into the clock signal. The clock signal can also introduce

noise into the analog path if not isolated from that path.

Best dynamic performance is obtained when the exposed

pad at the back of the package has a good connection to

ground. This is because this path from the die to ground is a

lower impedance than that offered by the package pins.

10.0 COMMON APPLICATION PITFALLS

Allowing loose power supply voltage tolerance. The

ADC081000 is specified for operation between 1.8 Volts to

2.0 Volts. Using a 1.8 Volt power supply then implies the

need for no negative tolerance. The best solution is to use an

adjustable linear regulator such as the LM317 or LM1086 set

for 1.9V as discussed in Section 7.1.

Driving the inputs (analog or digital) beyond the power

supply rails. For device reliability, all inputs should not go

more than 150 mV below the ground pins or 150 mV above

the supply pins. Exceeding these limits on even a transient

basis may not only cause faulty or erratic operation, but may

impair device reliability. It is not uncommon for high speed

digital circuits to exhibit undershoot that goes more than a

volt below ground. Controlling the impedance of high speed

lines and terminating these lines in their characteristic im-

pedance should control overshoot.

Care should be taken not to overdrive the inputs of the

ADC081000. Such practice may lead to conversion inaccu-

racies and even to device damage.

Incorrect analog input common mode voltage in the d.c.

coupled mode. As discussed in Sections 1.3 and 3.0, the

Input common mode voltage must remain within 50 mV of

the V

CMO output and track that output, which has a variability

with temperature that must also be tracked. Distortion per-

formance will be degraded if the input common mode volt-

age is more than 50 mV from V

CMO.

Using an inadequate amplifier to drive the analog input.

Use care when choosing a high frequency amplifier to drive

the ADC081000 as many high speed amplifiers will have

higher distortion than will the ADC081000, resulting in over-

all system performance degradation.

Driving the V

BG pin to change the reference voltage. As

mentioned in Section 1.3, the reference voltage is intended

to be fixed to provide one of two different full-scale values

(600 mV

P-P and 800 mVP-P). Over driving this pin will not

change the full scale value, but can otherwise upset opera-

tion.

Driving the clock input with an excessively high level

signal. The ADC clock level should not exceed the level

described in the Operating Ratings Table or the input offset

error could increase.

Inadequate clock levels. As described in Section 4.0, insuf-

ficient clock levels can result in poor performance. Excessive

clock levels could result in the introduction of an input offset.

Using an excessively long clock signal trace, or having

other signals coupled to the clock signal trace. This will

cause the sampling interval to vary, causing excessive out-

put noise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described in

Section 7.2, it is important to provide an adequate heat

removal to ensure device reliability. This can either be done

with adequate air flow or the use of a simple heat sink built

into the board. The backside pad should be grounded for

best performance.

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