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AND8048 Datasheet(PDF) 1 Page - ON Semiconductor |
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AND8048 Datasheet(HTML) 1 Page - ON Semiconductor |
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1 / 8 page ![]() © Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 0 1 Publication Order Number: AND8048/D AND8048/D SPICE Device Model NTHD5905T1 Dual P–Channel 1.8 V (G–S) MOSFET CHARACTERISTICS • P–Channel Vertical DMOS • Macro–Model (Sub–circuit) • Level 3 MOS • Applicable for both Linear and Switch Mode • Applicable over a –55 to 125°C Temperature Range • Models Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached SPICE Model describes typical electrical characteristics of the p–channel vertical DMOS. The sub–circuit model was extracted and optimized over a 25 °C to 125 °C temperature range under pulse conditions for 0 to –5 volts gate drives. Saturated output impedance model accuracy has been maximized for gate biases near threshold. A novel gate–to–drain feedback capacitor network is used to model gate charge characteristics while avoiding convergence problems of switched Cgd model. Model parameter values are optimized to provide a best fit to measure electrical data and are not intended as an exact physical description of a device. Figure 1. Model Sub–circuit R M 1 2 3 4 G S D DB CGS M This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. http://onsemi.com APPLICATION NOTE |
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