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TSZ02201-0212ACB00200-1-2

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21.Jan.2022 Rev.001

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TSZ22111

• 15 • 001

BD62012BFS

Operational Notes - continued

10. Regarding the Input Pin of the IC

Do not force voltage to the input pins when the power does not supply to the IC. Also, do not force voltage to the input pins

that exceed the supply voltage or in the guaranteed the absolute maximum rating value even if the power is supplied to the

IC.

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.

P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode or

transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference

among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to operate, such as

applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be avoided.

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with temperature

and the decrease in nominal capacitance due to DC bias and others.

Figure 42. Example of Monolithic IC structure

Resistor

Pin A

Parasitic

Elements

P

+

P

+

N

N

N

N

P

P Substrate

GND

Parasitic

Elements

Pin A

Transistor(NPN)

Parasitic

Elements

P Substrate

GND

Pin B

C

B

GND

P

+

N

N

N

P

P

+

N

N

E

Pin B

E

C

B

N Region

close-by

Parasitic

Elements