Update-DR. A falling edge on TCK while in the

Update-DR state latches the data from the shift regis-

ter path of the test data registers into a set of output

latches. This prevents changes at the parallel output

because of changes in the shift register. On the rising

edge of TCK, the controller goes to the Run-Test/Idle

state if TMS is LOW or it goes to the Select-DR-Scan

state if TMS is HIGH.

Select-IR-Scan. All test data registers retain their previ-

ous state. The Instruction Register remains unchanged

during this state. With TMS LOW, a rising edge on TCK

moves the controller into the Capture-IR state. TMS

HIGH during a rising edge on TCK puts the controller

back into the Test-Logic-Reset state.

Capture-IR. The Capture-IR state is used to load the

shift register in the Instruction Register with a fixed

value. This value is loaded on the rising edge of TCK. If

TMS is HIGH on the rising edge of TCK, the controller

enters the Exit1-IR state. If TMS is LOW on the rising

edge of TCK, the controller enters the Shift-IR state.

Shift-IR. In this state, the shift register in the Instruction

register is connected between TDI and TDO and shifts

data one stage for every rising edge of TCK toward the

TDO serial output while TMS is LOW. The parallel out-

puts of the Instruction Register as well as all test data

registers remain at their previous states. A rising edge

on TCK with TMS HIGH moves the controller to the

Exit1-IR state. A rising edge on TCK with TMS LOW

keeps the controller in the Shift-IR state while moving

data one stage through the Instruction Shift Register.

Exit1-IR. A rising edge on TCK with TMS LOW puts

the controller in the Pause-IR state. If TMS is HIGH on

the rising edge of TCK, the controller enters the

Update-IR state.

Pause-IR. Shifting of the Instruction shift register is halt-

ed temporarily. With TMS HIGH, a rising edge on TCK

puts the controller in the Exit2-IR state. The controller

remains in the Pause-IR state if TMS is LOW during a

rising edge on TCK.

Exit2-IR. A rising edge on TCK with TMS HIGH puts the

controller in the Update-IR state. The controller loops

back to Shift-IR if TMS is LOW during a rising edge of

TCK in this state.

Update-IR. The instruction code that has been shifted

into the Instruction shift register is latched to the paral-

lel outputs of the Instruction Register on the falling

edge of TCK as the controller enters this state. Once

latched, this instruction becomes the current instruc-

tion. A rising edge on TCK with TMS LOW puts the con-

troller in the Run-Test/Idle state. With TMS HIGH, the

controller enters the Select-DR-Scan state.

Instruction Register

The Instruction Register contains a shift register as well

as a latched parallel output and is 4 bits in length. When

the TAP controller enters the Shift-IR state, the Instruction

shift register is connected between TDI and TDO. While

in the Shift-IR state, a rising edge on TCK with TMS LOW

shifts the data one stage toward the serial output at TDO.

A rising edge on TCK in the Exit1-IR state or the Exit2-IR

state with TMS HIGH moves the controller to the Update-

IR state. The falling edge of that same TCK latches the

data in the Instruction shift register to the Instruction

Register parallel output. Instructions supported by the

DS4550 and its respective operational binary codes are

SAMPLE/PRELOAD. This is a mandatory instruction

for the IEEE 1149.1 specification that supports two

functions. The digital I/Os of the device can be sam-

pled at the Boundary Scan test data register without

interfering with the normal operation of the device by

using the Capture-DR state. SAMPLE/PRELOAD also

allows the device to shift data into the Boundary Scan

test data register through TDI using the Shift-DR state.

BYPASS. When the BYPASS instruction is latched into

the Instruction register, TDI connects to TDO through

the 1-bit Bypass test data register. This allows data to

pass from TDI to TDO without affecting the device’s

normal operation.

EXTEST. This instruction allows testing of all intercon-

nections to the device. When the EXTEST instruction is

latched in the Instruction register, the following actions

occur. Once enabled through the Update-IR state, the

parallel outputs of all digital output pins are driven. The

Boundary Scan test data register is connected between

TDI and TDO. The Capture-DR samples all digital

inputs into the Boundary Scan test data register.

Expander Plus Memory

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11

INSTRUCTION

SELECTED

REGISTER

INSTRUCTION

CODE

SAMPLE/PRELOAD

Boundary Scan

0010

BYPASS

Bypass

1111

EXTEST

Boundary Scan

0000

CLAMP

Bypass

0011

HIGHZ

Bypass

0100

IDCODE

Identification

0001

ADDRESS

Memory Address

1001

READ

Memory Read

1010

WRITE

Memory Write

1011