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74HC595 Datasheet(PDF) 18 Page - NXP Semiconductors |
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74HC595 Datasheet(HTML) 18 Page - NXP Semiconductors |
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18 / 28 page  2003 Jun 25 18 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 tW shift clock pulse width HIGH or LOW see Fig.7 4.5 20 −− ns storage clock pulse width HIGH or LOW see Fig.8 4.5 20 −− ns master reset pulse width LOW see Fig.10 4.5 25 −− ns tsu set-up time DS to SH_CP see Fig.9 4.5 20 −− ns set-up time SH_CP to ST_CP see Fig.8 4.5 20 −− ns th hold time DS to SH_CP see Fig.9 4.5 3 −− ns trem removal time MR to SH_CP see Fig.10 4.5 13 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 24 −− MHz Tamb = −40 to +125 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 4.5 −− 63 ns propagation delay ST_CP to Qn see Fig.8 4.5 −− 60 ns tPHL propagation delay MR to Q7’ see Fig.10 4.5 −− 60 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 4.5 −− 53 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 4.5 −− 45 ns tW shift clock pulse width HIGH or LOW see Fig.7 4.5 24 −− ns storage clock pulse width HIGH or LOW see Fig.8 4.5 24 −− ns master reset pulse width LOW see Fig.10 4.5 30 −− ns tsu set-up time DS to SH_CP see Fig.9 4.5 24 −− ns set-up time SH_CP to ST_CP see Fig.8 4.5 24 −− ns th hold time DS to SH_CP see Fig.9 4.5 3 −− ns trem removal time MR to SH_CP see Fig.10 4.5 15 −− ns fmax maximum clock pulse frequency SH_CP or ST_CP see Figs 7 and 8 4.5 20 −− MHz SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) |
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