AD5764CSU datasheet(18/27 Pages) AD

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AD5764

Preliminary Technical Data

Rev. PrC 21-Oct-04| Page 18 of 28

VOUT

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

VREFIN

SYNC

INPUT

SCLK

Figure 9. Simplified Serial Interface showing input loading

circuitry for one DAC Channel

TRANSFER FUNCTION

Table ? Shows the ideal input code to output voltage relationship

for the AD5764 for both straight binary and twos complement

data coding.

Digital Input

Analog Output

Straight Binary Data Coding

MSB

LSB

VOUT

1111

+2 VREF x (32767/32768)

1000

0000

0001

+2 VREF x (1/32768)

1000

0000

0 V

0111

1111

-2 VREF x (1/32768)

0000

-2 VREF x (32767/32768)

Twos Complement Data Coding

MSB

LSB

VOUT

0111

1111

+2 VREF x (32767/32768)

0000

0001

+2 VREF x (1/32768)

0000

0 V

1111

-2 VREF x (1/32768)

1000

0000

-2 VREF x (32767/32768)

The output voltage expression is given by

⎥⎦

⎤

⎢⎣

⎡

−

65536

REFIN

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.

VREFIN is the reference voltage applied at the REFIN pin.

ASYNCHRONOUS CLEAR (CLR)

CLR is an active low, level sensitive clear that allows the outputs

to be cleared to either 0 V (straight binary coding) or negative

full scale (twos complement coding). It is necessary to maintain

CLR low for a minimum amount of time (refer to Figure 3) for

the operation to complete. When the CLR signal is returned

high, the output remains at the cleared value until a new value is

programmed. The CLR signal has priority over LDAC and

SYNC. A clear can also be initiated through software by writing

the command 0x04XXXX to the AD5764.

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