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CLC020 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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CLC020 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 15 page ![]() Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD−VSS) 6.0V CMOS/TTL Input Voltage (V I) −0.5V to (V DD + 0.5V) CMOS/TTL Output Voltage (V O) −0.5V to (V DD + 0.5V) CMOS/TTL Input Current (single input) V I =VSS −0.5V −5 mA V I =VDD +0.5V +5 mA Input Current, Other Inputs ±1mA CMOS/TTL Output Source/Sink Current ±10 mA SDO Output Source Current 20 mA Package Thermal Resistance θ JA 28-lead PLCC 85˚C/W θ JC 28-lead PLCC 35˚C/W Storage Temp. Range −65˚C to +150˚C Junction Temperature +150˚C Lead Temperature (Soldering 4 Sec) +260˚C ESD Rating (HBM) >2.5 kV ESD Rating (MM) >200 V Transistor Count 33,400 Recommended Operating Conditions Supply Voltage (V DD−VSS) 5.0V ±10% CMOS/TTL Input Voltage V SS to VDD P CLK Frequency Range 10 to 40MHz P CLK Duty Cycle 45 to 55% D N and PCLK Rise/Fall Time 1.0 to 3.0 ns Maximum DC Bias on SDO pins 3.0V ±10% Operating Free Air Temperature (T A) 0˚C to +70˚C DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units V IH Input Voltage High Level D0 through D9, P CLK, TPG_EN and Sync. Detect Enable 2.0 V DD V V IL Input Voltage Low Level V SS 0.8 V I IH Input Current High Level V IH =VDD +40 +60 µA I IL Input Current Low Level V IL =VSS -1 -20 µA V OH CMOS Output Voltage High Level I OH = −10 mA Lock Detect, Test Out 2.4 4.7 V DD V V OL CMOS Output Voltage Low Level I OL = +10 mA 0.0 0.3 V SS + 0.5V V V SDO Serial Driver Output Voltage R L =75 Ω 1%, R REF = 1.69 k Ω 1%, Figure 2 SDO, SDO 700 800 900 mV P-P I DD Power Supply Current, Total R L =75 Ω 1%, R REF = 1.69 k Ω 1%, P CLK = 27 MHz, Figure 2, NTSC Colour Bar Pattern 47 60 mA AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units BR SDO Serial data rate R L =75 Ω, AC coupled, (Note 5) SDO, SDO 100 400 Mbps F PCLK Reference Clock Input Frequency P CLK 10 40 MHz Reference Clock Duty Cycle P CLK 45 50 55 % t r,tf Rise time, Fall time 10%–90% D N,PCLK 1.0 1.5 3.0 ns t j Serial output jitter 270 Mbps,Figure 2, (Note 6) SDO, SDO 220 ps P-P t jit Serial output jitter (Notes 4, 5) 100 200 ps P-P t r,tf Rise time, Fall time 20%–80%, (Notes 4, 5) 500 800 1500 ps Output overshoot 1% t LOCK Lock time 270 Mbps, (Notes 5, 7) 75 µs t SU Setup time Figure 3 D N to PCLK 32 ns www.national.com 3 |
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