MP8820

6

Rev. 1.00

1111111

00000000

CODE

+ Gain Error

+ INL Error

Ideal + Offset

Ideal

Actual

Offset

– Gain Error

– INL Error

Figure 3. Transfer Characteristics

with Error Terms

The sign of the digital output code is determined by whether

then the seven bit conversion occurs in the positive half of the

curs in the negative half of the transfer function.

Table 1. shows

the digital codes that result from different input voltages.

CODE

00000000

–FS

00000001

–FS + 1LSB

.

.

.

.

10000000

.

.

.

.

11111110

FS – 2LSB

11111111

FS – 1LSB

Table 1. Digital Codes vs. Input Voltage

The MP8820 uses a stand alone

µP interface. The user starts

a conversion by taking WR low. While WR is low, the input track

WR, the input is sampled. The rising edge of WR enables a state

machine which steps the ADC through a conversion.

The output port is held in high impedance state during the

conversion period. The operating timing diagrams are shown in

Figure 4.

Data Valid for Sample N-1

Mux Address Valid

for Sample N

Data Valid for Sample N

Figure 4. Operating Timing Diagrams

WR

DB0-DB7

A0-A2

Analog To Digital Conversion

The MP8820 converts analog voltages into 256 digital codes

by encoding the outputs of 15 coarse and 15 fine comparators.

When WR goes low, the input sample and hold circuitry is en-

abled. The track and hold circuit will follow the output of the 8

channel mux. The channel that is to be converted does not need

rising edge of WR. So, while WR is low, the track and hold circuit

only has to follow the analog input to be converted for 150 ns.

The analog input is sampled at a time equal to the aperture

accounts for internal propagation delays. The mux address

ing the rising edge of WR. For the analog timing diagram, see

Figure 5.