MP8820

7

Rev. 1.00

Figure 5. Analog Timing Diagram

Inside the ADC is a series of comparators that sample the

analog input and compare it against a resistor tap voltage. A

state machine generates the internal clocks necessary to con-

trol the comparators,

φc (CLK high) and φs (CLK low = sample).

See

Figure 6. The rising edge of the CLK input marks the end of

the sampling phase,

φs. On φs, the analog input voltage is

sampled and stored across capacitor C1. The switches con-

trolled by

φs are opened prior to the compare which is done on

clock phase

φc. The voltage stored on the capacitor is then

high or low and the result is latched.

Figure 6. Comparator Block Diagram

φS

φC

C1

φS

φC

Latch

The analog to digital conversion happens in four phases.

During the first phase, the analog input is sampled. During the

second phase, this input is compared against the reference lad-

der to determine the MSBs. After the MSBs are determined, a

subrange is set for phase three, the conversion of the LSBs.

Once all the bits have been derived, the MP8820 performs a

correction. The valid data is then ready at the output. The timing

diagram is shown in

Figure 7.

Figure 7. Internal ADC Timing Diagram

φSN

φSN+1

φCMSBs

φCLSBs

φCORR

Data Sample N-1

Data Sample N

Sample

Compare

MSBs

Compare

LSBs

Correction

Data

The input mux operates as a standard 8 to 1 decoder. One of

eight analog inputs is selected depending on the condition of the

address pins A0, A1, and A2. The mux can change address af-

dress should be held constant for at least 150 ns before the ris-

ing edge of WR.

Function

WR

XINT

A0

A1

A2

↓

1

X

X

X

↑

1

X

X

X

Start Convert

↑

1

X

X

X

Conversion Complete

1

↓

X

X

X

Enable Output Data

X

0

X

X

X

X

X

0

0

0

X

X

0

0

1

X

X

0

1

0

X

X

0

1

1

X

X

1

0

0

X

X

1

0

1

X

X

1

1

0

X

X

1

1

1

Table 2. Truth Table