STM32F103CBU7TR datasheet(70/116 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F103x8, STM32F103xB

70/116

DS5319 Rev 18

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 42 are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized in Table 9.

Refer to Section 5.3.12 for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO).

Table 42. SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall time Capacitive load: C = 30 pF

DuCy(SCK)

SPI slave input clock



duty cycle

Slave mode

tsu(NSS)(1)

1. Evaluated by characterization, not tested in production, unless otherwise specified.

NSS setup time

Slave mode

4 tPCLK

th(NSS)(1) NSS hold time

Slave mode

2 tPCLK

tw(SCKH)(1)

tw(SCKL)(1)

SCK high and low time

Master mode, fPCLK = 36 MHz,

presc = 4

tsu(MI) (1)

tsu(SI)(1)

Data input setup time

Master mode

Slave mode

th(MI) (1)

Data input hold time

Master mode

th(SI)(1)

Slave mode

ta(SO)(1)(2)

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate

the data.

Data output access time

Slave mode, fPCLK = 20 MHz

3 tPCLK

tdis(SO)(1)(3)

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put

the data in Hi-Z.

Data output disable time

Slave mode

tv(SO) (1) Data output valid time

Slave mode (after enable edge)

tv(MO)(1) Data output valid time

Master mode (after enable edge)

th(SO)(1)

Data output hold time

Slave mode (after enable edge)

th(MO)(1)

Master mode (after enable edge)

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