LT3045 datasheet(41/45 Pages) AD

41 / 45 page

Data Sheet

LT3097

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 41 of 45

on thermal resistance and high thermal conductivity test boards,

refer to JEDEC standard JESD-51, JESD51-7, and JESD51-12.

Achieving low thermal resistance necessitates careful PCB layout.

Table 5. Measured Thermal Resistance for DFN Package

Copper Area

Board Area

Thermal

Resistance (θJA)

Top Side1

Bottom Side

2500 mm2

34°C/W

1000 mm2

2500 mm2

35°C/W

225 mm2

2500 mm2

36°C/W

1 The device is mounted on the topside.

CALCULATING JUNCTION TEMPERATURE

For example, given a positive output voltage of 3.3 V, a positive

input voltage of 5 V ± 5%, a positive output current range from 1

mA to 500 mA, a negative output voltage of −3.3 V, a negative input

voltage of −5 V ± 5%, a negative output current range from 1 mA to

500 mA, and a maximum ambient temperature of 50°C, what is the

maximum junction temperature?

The power dissipation of the positive side of the LT3097 is the

following:

IOUTPMAX× VINPMAX−VOUTP +IGNDP

×VINPMAX

(8)

where:

IOUTP(MAX) = 500 mA.

VINP(MAX) = 5.25 V.

IGNDP (at IOUTP = 500 mA and VINP = 5.25 V) = 12.5 mA.

Therefore, PDISS-POSITIVE = 0.5 A × (5.25 V − 3.3 V) + 12.5 mA ×

5.25 V = 1 W.

The power dissipation of the negative side of the LT3097 is the

following:

IOUTNMAX× VINNMAX−VOUTN +IGNDN

×VINNMAX

(9)

where:

IOUTN(MAX) = 500 mA.

VINN(MAX) = −5.25 V.

IGNDN (at IOUTN = 500 mA and VINN = −5.25 V) = 9 mA.

Therefore, PDISS-NEGATIVE = −0.5 A × (−5.25 V + 3.3 V) + 9 mA ×

5.25 V = 1.02 W.

The total power equals PTOTAL = PDISS-POSITIVE + PDISS-NEGATIVE,

which is 2.02W.

Using a DFN package, the thermal resistance is in the range of

34°C/W to 37°C/W, depending on the copper area. Therefore, the

junction temperature rise above ambient approximately equals 2.02

W × 35°C/W = 70.7°C.

The maximum junction temperature equals the maximum ambient

temperature plus the maximum junction temperature rise above

ambient, which calculates as follows:

TJMAX=50°C+70.7°C=120.7°C

(10)

OVERLOAD RECOVERY

Like many IC power regulators, the LT3097 incorporates SOA pro-

tection. The SOA protection activates at input-to-output differential

voltages greater than 12 V for the positive regulator and 7V for

the negative regulator. The SOA protection decreases the current

limit because the input-to-output differential increases and keeps

the power transistor inside a safe operating region for all values

of input-to-output voltages up to the Absolute Maximum Ratings of

the LT3097. The LT3097 provides some level of output current for

all values of input-to-output differentials. See the Figure 56/Figure

57. When power is first applied, and the input voltage rises, the

output follows the input and keeps the input-to-output differential

low to allow the LDO regulator to supply the large output current

and startup into high-current loads.

Due to current-limit foldback, however, at high-input voltages, a

problem can occur if the output voltage is low, and the load current

is high. Such situations occur after the removal of a short-circuit

or if the ENP/UVP or ENN/UVN pins are pulled high after the

input voltage is already turned on. The load-line, in such cases,

intersects the output-current profile at two points. As a result, the

regulator now has two stable operating points. With this double

intersection, the input-power supply may need to be cycled down

to zero and brought back up again to allow the output to recover.

Other LDO regulators with foldback current-limit protection (such as

the LT3042 and LT3093) also exhibit this phenomenon; therefore, it

is not unique to the LT3097.

LT3045 Datasheet(PDF) 41 Page - Analog Devices

LT3045 Datasheet(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL