845264 datasheet(15/24 Pages) RENESAS

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REVISION B 07/20/15

FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR

845264 DATA SHEET

Schematic Example

Figure 3 shows an example of 845264 application schematic. In this

example, the device is operated at VDD = VDDA = 3.3V. The schematic

example focuses on functional connections and is not configuration

specific. Refer to the pin description and functional tables in the

datasheet to ensure that the logic control inputs are properly set.

A 12pF parallel resonant 25MHz crystal is used. For this device, the

crystal load capacitors are required for proper operation. The load

capacitance, C1 = C2 = 2pF, are recommended for frequency

accuracy. Depending on the variation of the parasitic stray capacity

of the printed circuit board traces between the crystal and the

XTAL_IN and XTAL_OUT pins, the values of C1 and C2 might require

a slight adjustment to optimize the frequency accuracy. Crystals with

other load capacitance specifications can be used, but this will

require adjusting C1 and C2. When designing the circuit board,

return the capacitors to ground though a single point contact close to

the package. Two Fox crystal options are shown in the schematic for

design flexibility.

The ePAD provides a low thermal impedance connection between

the internal device and the PCB. It also provides an electrical

connection to the die and must be connected to ground.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The 845264 provides separate

power supplies to isolate any high switching noise from coupling into

the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1uF capacitor in each power pin filter should be placed on the

device side. The other components can be on the opposite side of the

PCB.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for a wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supplies frequencies, it is recommended that component

values be adjusted and if required, additional filtering be added.

Additionally, good general design practices for power plane voltage

stability suggests adding bulk capacitance in the local area of all

devices.

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