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845264 Datasheet(PDF) 2 Page - Renesas Technology Corp

Part # 845264
Description  FemtoClock®Crystal-to-CML Clock Generator
PDF  24 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

845264 Datasheet(HTML) 2 Page - Renesas Technology Corp

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REVISION B 07/20/15
2
FEMTOCLOCK®CRYSTAL-TO-CML CLOCK GENERATOR
845264 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 2
nQA0, QA0
Output
Bank A differential clock output pair. CML interface levels.
3, 17
VDD
Power
Core supply pins.
4
nOEA
Input
Pulldown
Output enable pin for Bank A outputs. See Table 3E for function.
LVCMOS/LVTTL interface levels.
5, 6, 7, 8, 9,
16, 25, 32
nc
Unused
Do not connect.
10
VDDA
Power
Analog supply pin.
11
nBYPASS
Input
Pullup
PLL bypass pin. See Table 3D for function. LVCMOS/LVTTL interface levels.
12
REF_CLK
Input
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
13, 29
GND
Power
Power supply ground.
14,
15
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
18,
19
FSELB0,
FSELB1
Input
Pulldown
Output frequency divider select enable pins for Bank B outputs.
See Table 3C for function. LVCMOS/LVTTL interface levels.
20,
21
FSELA0,
FSELA1
Input
Pulldown
Output frequency divider select enable pins for Bank A outputs.
See Table 3B for function. LVCMOS/LVTTL interface levels.
22
REF_SEL
Input
Pulldown
PLL reference clock select pin. See Table 3A for function.
LVCMOS/LVTTL interface levels.
23, 24
QB0, nQB0
Output
Bank B differential clock output pair. CML interface levels.
26
nOEB
Input
Pulldown
Output enable pin for Bank B outputs. See Table 3F for function.
LVCMOS/LVTTL interface levels.
27, 28
nQB1, QB1
Output
Bank B differential clock output pair. CML interface levels.
30, 31
nQA1, QA1
Output
Bank A differential clock output pair. CML interface levels.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input
Capacitance
nBYPASS,
REF_SEL,
nOEA, nOEB,
FSELB0, FSELB1,
FSELA0, FSELA1
4pF
RPULLDOWN
Input Pulldown Resistor
51
k
RPULLUP
Input Pullup Resistor
51
k



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