R31DS0110EU0100 Rev.1.00

Page 3

Jan 18, 2022

9UMS9633B Datasheet

1. Pin Information

1.1

Pin Assignments

Note:

* indicates inputs with internal pull-up of ~10kΩ to 3.3V.

Figure 2. 48-VFQFPN, 6 × 6 mm, Top View

1.2

Pin Descriptions

Pin Number

Pin Name

Pin Type

Description

1

CPU_STOP#

Input

Stops CPU0 clock when enabled.

2

CLKPWRGD#/PD_3.3

Input

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch

inputs are valid and are ready to be sampled. This is an active low input.

Asynchronous active high input pin used to place the device into a power down

state.

3

X2

Output

Crystal output, Nominally 14.318MHz

4

X1

Input

Crystal input, Nominally 14.318MHz.

5

VDDREF_3.3

Power

Power pin for the XTAL and REF clocks, nominal 3.3V.

6

REF

Output

14.318MHz reference clock.

7

GNDREF

Power

Ground pin for the REF outputs.

8

VDDCORE_3.3

Power

3.3V power for the PLL core.

9

FSC_L

Input

Low threshold input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values.

10

TEST_MODE

Input

TEST_MODE is a real time input to select between Hi-Z and REF/N divider

mode while in test mode. Refer to Test Clarification table.

48 47 46 45 44 43 42 41 40 39 38 37

CPU_STOP# 1

36 *CR#2

CLKPWRGD#/PD_3.3 2

35 SRCT2_LPR

X2 3

34 SRCC2_LPR

X1 4

33 GNDSRC

VDDREF_3.3 5

32 SRCT1_LPR

REF 6

31 SRCC1_LPR

GNDREF 7

30 VDDIO_1.5

VDDCORE_3.3 8

29 VDDCORE_3.3

FSC_L 9

28 *CR#1

TEST_MODE 10

27 SRCT0_LPR

TEST_SEL 11

26 SRCC0_LPR

SCLK_3.3 12

25 GNDSRC

13 14 15 16 17 18 19 20 21 22 23 24

9UMS9633