Electronic Components Datasheet Search
  English  ▼

X  

70V06 Datasheet(PDF) 21 Page - Renesas Technology Corp

Part # 70V06
Description  HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
PDF  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

70V06 Datasheet(HTML) 21 Page - Renesas Technology Corp

Back Button 70V06 Datasheet HTML 16Page - Renesas Technology Corp 70V06 Datasheet HTML 17Page - Renesas Technology Corp 70V06 Datasheet HTML 18Page - Renesas Technology Corp 70V06 Datasheet HTML 19Page - Renesas Technology Corp 70V06 Datasheet HTML 20Page - Renesas Technology Corp 70V06 Datasheet HTML 21Page - Renesas Technology Corp 70V06 Datasheet HTML 22Page - Renesas Technology Corp 70V06 Datasheet HTML 23Page - Renesas Technology Corp 70V06 Datasheet HTML 24Page - Renesas Technology Corp  
Zoom Inzoom in Zoom Outzoom out
 21 / 24 page
background image
6.42
70V06L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
21
Feb.07.20
Using Semaphores-Some Examples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT70V06’sDual-PortSRAM.Saythe16Kx8
SRAM was to be divided into two 8K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore0couldbeusedtoindicatethesidewhichwouldcontrolthe
lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
Totakearesource,inthisexamplethelower8KofDual-PortSRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
back rather than a one), the left processor would assume control of the
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
the resourceaftertheleftprocessor,itwouldreadbackaoneinresponse
to the zero it had attempted to write into Semaphore 0. At this point, the
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 8K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
D0
2942 drw 19
D
Q
WRITE
D0
D
Q
WRITE
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
LPORT
RPORT
SEMAPHORE
READ
SEMAPHORE
READ
,
Figure 4. IDT70V06 Semaphore Logic
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
PortSRAMorothersharedresourcesintoeightparts.Semaphorescan
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assignedSRAMsegmentsatfullspeed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com