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L9969S Datasheet(PDF) 51 Page - STMicroelectronics

Part # L9969S
Description  Automotive chip for single and dual H-bridge
PDF  70 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9969S Datasheet(HTML) 51 Page - STMicroelectronics

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Table 39. Register SPECIAL_REG
Bit
7
6
5
4
3
2
1
0
Bit-Name Not specified Not specified
DCmatching
OLDAFILTER
Not specified
SR0 SR1 Reserved
POR
0
0
0
1
0
0
0
1
SPIR
0
0
0
1
0
0
0
1
ENDISR
x
x
x
x
x
x
x
x
DISR
x
x
x
x
x
x
x
x
RDR
x
x
x
x
x
x
x
x
Controller access: read/write
(write-access: WR_SPECIAL)
(read-access: RD_SPECIAL)
Bit
Name
Description
7
Not specified
6
Not specified
5
DCmatching
‘0’: EMC optimized switching behavior
‘1’: exact duty cycle matching
(latched) (r/w)
4
OLDAFILTER
‘1’: Open Load in on state detected after one retry
(latched) (r/w)
‘0’: Open Load in on detected after 40 ms
3
Not specified
2
SR0
See Table 40 below
(latched) (r/w)
1
SR1
0
Reserved
r/w for special use
(latched) (r/w)
Table 40. Slew Rate bits (SPECIAL_REG)
SR1
SR0
Description
Remark
0
0
Slow slew rate
Default slew rate(1)
0
1
Fast slew rate
Fast slew rate(1)
1
0
Very fast slew rate 1
Very fast slew rate(1)
1
1
Very fast slew rate 2
1. See Section 3.2.4.3 Power stage switching parameters
3.2.7.7
Electrical characteristics
The timing of the H-bridge is defined as follows:
•
The change at output (SO) is forced by the rising edge of the SCK signal.
•
The input signal (SI) is latched on the falling edge of the SCK signal.
•
The data received during a write access are written into the internal registers at the rising edge of the NSS
signal, if exactly 16 SPI clock pulses have been counted during NSS = active.
•
The data transmitted during a read access is reflecting the status of the chip just before the SPI read
instruction.
•
There is only a SPI communication with a clock; without clock, the H-bridge should not react on SO.
L9969x
Functional behavior in detail
DS14029 - Rev 3
page 51/70



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