Data Sheet

LT4322

analog.com

Rev. 0

11 of 29

For DC input supplies, VDDC must be driven from a DC supply voltage that is at least 9.5V higher than the ANODE/VSSA

voltage. Alternatively, VDDA can also be driven directly from a DC power supply whose voltage ranges from 9V to 14V

above VSSA. In this case, the LDO is not used, and users must connect VDDC to VSSA.

Internal undervoltage lockout (UVLO) circuitry drives the GATE pin to VSSA until VDDA has enough voltage to operate

properly. During this time, there is still a conduction path from input to output via the body diode of the external

MOSFET.

Steady-State Operation

Figure 19 shows the MOSFET gate and output voltage waveforms in steady-state operation for the full-bridge rectifier

circuit shown in Figure 20. The input power supply waveform VIN is a 120VRMS, 60Hz sine wave. As VIN nears its peak

voltage on positive half cycles, bottom side gate VBG1 and top side gate VTG1 are driven 12V above their respective

VSSA voltages, turning on M1 and M2 and charging VOUT to the peak VIN voltage. On negative half-cycles, bottom-side

gate VBG2 and top-side gate VTG2 are driven 12V above their respective VSSA voltages, turning on M3 and M4 and

charging VOUT to the peak VIN voltage.

Power MOSFETs M1 to M4 conduct high current to the output with a much lower forward voltage drop than a

Schottky diode, resulting in much higher efficiency and a lower temperature rise.

Figure 19. Full-Bridge Waveforms in Steady State

VTG1(30V/DIV)

VBG1(30V/DIV)

VOUT(30V/DIV)

VTG2(30V/DIV)