DA16200 datasheet(57/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

57 of 153

Figure 31 shows the timing diagram for the SDIO slave.

SDIO_CLK

SDIO_D[3:0]

SDIO_CMD

TCO.DLY

TDO.DLY

TCI.SU

TDI.SU

Figure 31: SDIO Slave Timing Diagram

Table 41 lists the timing parameters for the SDIO slave.

Table 41: SDIO Slave Timing Parameters

Parameter

Symbol

Min

Typ

Max

Unit

SDIO_CLK frequency

FSCLK

MHz

SDIO_CLK clock duty

SDIO_CMD input setup time

TCI.SU

SDIO_CMD output delay time

TCO.DLY

11 (Note 1)

SDIO_D[3:0] input setup time

TDI.SU

SDIO_D[3:0] output delay time

TDO.DLY

11 (Note 1)

Note 1

SDIO signals can set previous output from half cycle.

The SDIO interface requires pullup resistors to be connected between the signal lines and the supply

to enable communication.

DA16200

SD_CLK

SD_CMD

SD_D0

SD_D1

SD_D2

SD_D3

VDD_IO

Figure 32: SDIO Pull-up Resistor

Pull-up resistor values may vary based on the board layout.

DA16200 Datasheet(PDF) 57 Page - Renesas Technology Corp

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