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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

58 of 153

9.5

I2C Interface

9.5.1

I2C Master

DA16200 includes an I2C master module. Four ranges of clock speed are supported: standard (100

kHz), fast (400 kHz), fast plus (1.0 MHz) and High Speed (3.4 MHz) mode. Table 42 shows the pin

definition of the I2C master interface.

Table 42: I2C Master Pin Configuration

Pin Name

Pin Number

I/O

Function Name

QFN

fcCSP

GPIOA1

I2C_CLK

GPIOA5

GPIOA9

GPIOA0

I/O

I2C_SDA

GPIOA4

I/O

GPIOA8

I/O

Figure 33 shows the I2C timing diagram. The timing diagram is the same as that of the I2C slave

timing diagram.

THD;STA

SDA

SCL

TSU;DAT

THIGH

TLOW

THD;DAT

TVD;ACK

cont.

...

SDA

SCL

cont.

...

TSU;STA

THD;STA

TBUF

TSU;STO

Figure 33: I2C Master Timing Diagram

Table 43 lists the I2C master timing parameters.

Table 43: I2C Master Timing Parameters

Parameter

Symbol

Fast Mode

High Speed Mode

Unit

Min

Max

Min

Max

Operating Bus clock frequency

Fop_clk

120

MHz

SCL clock frequency

FSCLK

100

400

100

3400

(Note 2)

kHz

Clock Duty (Note 1)

Hold time of START

THD;STA

0.2

μs

Low period of the SCL clock

TLOW

1.27

0.55

μs

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