Output Power vs Supply Voltage

Chs1&3in Parallel Mode (Note 16)

f = 1kHz, R

Ω, 80kHz BW

Output Power vs Supply Voltage

All Chs in Parallel Mode (Note 16)

f = 1kHz, R

Ω, 80kHz BW

200898J6

200898J5

Note 15: Bridge mode graphs were taken using the demo board and inverting the signal to the channel 3 input.

Note 16: Parallel mode graphs were taken using the demo board connecting each output through a 0.1

Ω/3W resistor to the load.

Application Information

MUTE MODE

By placing a logic-high voltage on the mute pins, the signal

going into the amplifiers will be muted. If the mute pins are

connected to a logic-low voltage, the amplifiers will be in a

non-muted state. There are three mute pins, one for each

amplifier, so that one channel can be muted without muting

the other if the application requires such a configuration.

Refer to the Typical Performance Characteristics section

for curves concerning Mute Attenuation vs Mute Pin Voltage.

STANDBY MODE

The standby mode of the LM4734 allows the user to drasti-

cally reduce power consumption when the amplifiers are

idle. By placing a logic-high voltage on the standby pins, the

amplifiers will go into Standby Mode. In this mode, the

current drawn from the V

total for all amplifiers. The current drawn from the V

is typically 8mA. Clearly, there is a significant reduction in

idle power consumption when using the standby mode.

There are three Standby pins, so that one channel can be

put in standby mode without putting the other amplifier in

standby if the application requires such flexibility. Refer to

the Typical Performance Characteristics section for

curves showing Supply Current vs. Standby Pin Voltage for

both supplies.

UNDER-VOLTAGE PROTECTION

Upon system power-up, the under-voltage protection cir-

cuitry allows the power supplies and their corresponding

capacitors to come up close to their full values before turning

on the LM4734. Since the supplies have essentially settled

to their final value, no DC output spikes occur. At power

down, the outputs of the LM4734 are forced to ground before

the power supply voltages fully decay preventing transients

on the output.

OVER-VOLTAGE PROTECTION

The LM4734 contains over-voltage protection circuitry that

limits the output current while also providing voltage clamp-

ing. The clamp does not, however, use internal clamping

diodes. The clamping effect is quite the same as diodes

because the output transistors are designed to work alter-

nately by sinking large current spikes.

THERMAL PROTECTION

The LM4734 has a sophisticated thermal protection scheme

to prevent long-term thermal stress of the device. When the

temperature on the die exceeds 150˚C, the LM4734 shuts

down. It starts operating again when the die temperature

drops to about 145˚C, but if the temperature again begins to

rise, shutdown will occur again above 150˚C. Therefore, the

device is allowed to heat up to a relatively high temperature

if the fault condition is temporary, but a sustained fault will

cause the device to cycle in a Schmitt Trigger fashion be-

tween the thermal shutdown temperature limits of 150˚C and

145˚C. This greatly reduces the stress imposed on the IC by

thermal cycling, which in turn improves its reliability under

sustained fault conditions.

Since the die temperature is directly dependent upon the

heat sink used, the heat sink should be chosen so that

thermal shutdown is not activated during normal operation.

Using the best heat sink possible within the cost and space

constraints of the system will improve the long-term reliability

of any power semiconductor device, as discussed in the

Determining the Correct Heat Sink section.

DETERMlNlNG MAXIMUM POWER DISSIPATION

Power dissipation within the integrated circuit package is a

very important parameter requiring a thorough understand-

ing if optimum power output is to be obtained. An incorrect

maximum power dissipation calculation may result in inad-

equate heat sinking causing thermal shutdown and thus

limiting the output power.

Equation (1) shows the theoretical maximum power dissipa-

tion point for each amplifier in a single-ended configuration

where V

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