MPC9653 REVISION 4 FEBRUARY 4, 2013

7

©2013 Integrated Device Technology, Inc.

MPC9653 Data Sheet

3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR

Calculation of Part-to-Part Skew

The MPC9653 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC9653 are connected together, the maximum overall

timing uncertainty from the common PCLK input to any output

is:

tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()  CF

This maximum timing uncertainty consist of four

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

Figure 4. MPC9653 Max. Device-to-Device Skew

Due to the statistical nature of I/O jitter a RMS value (1

)

is specified. I/O jitter numbers for other confidence factors

(CF) can be derived from Table 8.

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation a I/

O jitter confidence factor of 99.7% (

 3) is assumed,

resulting in a worst case timing uncertainty from input to any

output of

– 197 ps to 297 ps (at 125 MHz reference frequency) relative

to PCLK:

tSK(PP) = [–17ps...117ps] + [–150ps...150ps] +

[(10ps

 –3)...(10ps  3)] + tPD, LINE(FB)

tSK(PP) = [–197ps...297ps] + tPD, LINE(FB)

Due to the frequency dependence of the I/O jitter, Figure 5 can be used for a

more precise timing performance analysis.

Figure 5. Max. I/O Jitter versus Frequency

Driving Transmission Lines

The MPC9653 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

 the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Motorola Application Note

AN1091. In most high performance clock networks

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

 resistance to VCC  2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9653 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 6 illustrates

an output driving a single series terminated line versus two

series terminated lines in parallel. When taken to its extreme

the fanout of the MPC9653 clock driver is effectively doubled

due to its capability to drive multiple lines.

Table 8. Confidence Factor CF

CF

Probability of clock edge within the distribution

 1

0.68268948

 2

0.95449988

 3

0.99730007

 4

0.99993663

 5

0.99999943

 6

0.99999999

tPD,LINE(FB)

tJIT()

+tSK(O)

—t(ý)

+t()

tJIT()

+tSK(O)

tSK(PP)

Max. skew

TCLKCommon

QFBDevice 1

Any QDevice 1

QFBDevice2

Any QDevice 2

30

20

10

0

FB =

 8

FB =

 4

25

35

45

55

65

75

85

95 105 115 125

Reference frequency [MHz]