MPC9653 REVISION 4 FEBRUARY 4, 2013

9

©2013 Integrated Device Technology, Inc.

MPC9653 Data Sheet

3.3 V 1:8 LVCMOS PLL CLOCK GENERATOR

Figure 9. PCLK MPC9653 AC Test Reference

Figure 10. Output-to-Output Skew tSK(O)

Figure 11. Propagation delay (t(PD), static phase offset)

Test Reference

Figure 12. Output Duty Cycle (DC)

Figure 13. I/O Jitter

Figure 14.

Figure 15.

Figure 16. Output Transition Time Test Reference

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

VCC

VCC 2

GND

VCC

VCC 2

GND

tSK(O)

VCC

VCC 2

GND

t(PD)

PCLK

FB_IN

PCLK

VPP = 0.8 V

VCMR =

VCC –1.3 V

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCC 2

GND

tP

T0

DC = tP/T0 x 100%

TJIT() = |T0–T1mean|

PCLK

PCLK

Ext_FB

The deviation in t0 for a controlled edge with respect to a T0

mean in a random sample of cycles

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

TN

TJIT(CC) = |TN–TN+1|

TN+1

The deviation in cycle time of a signal with respect to the ideal

period over a random sample of cycles

TJIT(PER) = |TN–1/f0|

T0

tF

tR

VCC=3.3 V

2.4

0.55