FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

547

Freescale Semiconductor, Inc.

TECHNICAL DATA

Order number: MPC96877

Rev 1, 08/2004

Product Preview

1.8 V PLL 1:10 Differential SDRAM

Recommended Applications

•

DDR II Memory Modules

•

Zero Delay Board fan-out

Features

•

1.8 V Phase Lock Loop Clock Driver for (DDR II) Applications

•

Spread Spectrum Clock Compatible

•

Operating Frequency: 100 MHz to 340 MHz

•

1 to 10 differential clock distribution (SSTL_18)

•

52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF (QFN)

•

52-lead Pb-free Package Available

•

External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs

to the Input Clocks

•

Single-Ended Input and Single-Ended Output Modes

•

Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300

•

Auto Power Down detect logic

Switching Characteristics

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Cycle-to-Cycle Jitter (>165 Mhz): 40 ps max.

•

Output-to-Output Skew: 40 ps max.

Functional Description

The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buffer

that distributes a differential clock input pair (CK, CK) to ten differential pairs of

clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK,

CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS),

and the analog power input (AVDD). When OE is low, the clock outputs, except

FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin

that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has

no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both

clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs,

independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the

PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and

the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK,

CK) within the specified stabilization time.

The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0

°C to 70°C.

MPC96877

VK SUFFIX

52-BALL FP-MAPBGA PACKAGE

CASE 1544-01

DDR II MEMORY

CLOCK / ZERO DELAY BUFFER

EP SUFFIX

40-PIN MLF/QFN PACKAGE

CASE 1545-01

AVAILABLE ORDERING OPTIONS

TA

52-Ball BGA

40-Pin QFN

0

°C to 70°C

MPC96877VK

(Pb-Free)

MPC96877EP

(Pb-Free)

DATA SHEET

MPC96877

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC96877

1

1.8 V PLL 1:10 Differential SDRAM

Clock Driver