MPC9893 REVISION 8 3/16/16

6

©2016 Integrated Device Technology, Inc.

MPC9893 Data Sheet

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

Table 8. AC Characteristics (VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, TA = –40° to 85°C)

(1)

1. AC characteristics apply for parallel output termination of 50

 to VTT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

FSEL=000x

FSEL=001x

FSEL=010x

FSEL=011x

FSEL=100x

FSEL=101x

FSEL=110x

FSEL=111x

15.0

30.0

40.0

30.0

60.0

15.0

30.0

60.0

25.0

50.0

66.6

50.0

100.0

12.5

50.0

100.0

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

PLL locked

fMAX

Maximum Output Frequency

FSEL=000x

FSEL=001x

FSEL=010x

FSEL=011x

FSEL=100x

FSEL=101x

FSEL=110x

FSEL=111x

60.0

60.0

60.0

30.0

60.0

7.5

15.0

30.0

200.0

200.0

200.0

100.0

200.0

25.0

50.0

100.0

MHz

MHz

MHz

MHz

MHz

MHz

MHz

MHz

PLL locked

frefDC

Reference Input Duty Cycle

40

60

%

tr, tf

CLK0, 1 Input Rise/Fall Time

1.0

ns

0.8 to 2.0 V

t()

Propagation Delay (static phase offset, CLKx to FB)

VCC=3.3 V5% and FSEL[0:2]=111

VCC=3.3 V5%

VCC=2.5 V5% and FSEL[0:2]=111

VCC=2.5 V5%

–60

–200

–125

–400

+50

+100

+25

+100

ps

ps

ps

ps

PLL locked

 t

Rate of Period Change (phase slew rate)

QAx outputs

QBx outputs (FSEL=xxx0)

QBx outputs (FSEL=xxx1)

150

150

300

ps/cycle

Failover switch

tsk(O)

Output-to-Output Skew(2)

(within bank)

(bank-to-bank)

(any output to QFB)

2. See application section for part-to-part skew calculation.

150

100

125

ps

ps

ps

DCO

Output Duty Cycle

45

50

55

%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns

0.55 to 2.4 V

tPLZ, HZ

Output Disable Time

10

ns

tPZL, LZ

Output Enable Time

10

ns

tJIT(CC)

Cycle-to-Cycle Jitter(3)

FSEL3=0

FSEL3=1

3. Cycle-to-cycle and period jitter depend on the VCO frequency and output configuration. See the application section.

225

425

ps

ps

See applications

section

tJIT(PER)

Period Jitter(3)

FSEL3=0

FSEL3=1

150

250

ps

ps

See applications

section

tJIT()

I/O Phase Jitter(4)

FB=4: FSEL[0:2]=100 or 111

RMS (1

)

FB=6: FSEL[0:2]=010

RMS (1

)

FB=8: FSEL[0:2]=001, 011, or 110

RMS (1

)

FB=16: FSEL[0:2]=000 or 101

RMS (1

)

4. I/O jitter depends on the VCO frequency and internal PLL feedback divider FB. See APPLICATIONS INFORMATION for more information

and for the calculation for other confidence factors than 1



40

50

55

70

ps

ps

ps

ps

See applications

section

BW

PLL Closed Loop Bandwidth(5)

FSEL=111x

5. –3dB point of PLL transfer characteristics.

0.8-4.0

MHz

tLOCK

Maximum PLL Lock Time

10

ms