MPC9893 REVISION 8 3/16/16

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©2016 Integrated Device Technology, Inc.

MPC9893 Data Sheet

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

Figure 13. Propagation Delay (t(), static phase

offset) Test Reference

Figure 14. Output Duty Cycle (DC)

Figure 12. Output-to-Output Skew tSK(O)

The pin-to-pin skew is defined as the worst case difference in propagation delay

between any similar delay path within a single device

VCC

VCC 2

GND

VCC

VCC 2

GND

tSK(O)

VCC

VCC 2

GND

VCC

VCC 2

GND

t()

CLK0,

CLK1

FB

The time from the PLL controlled edge to the noncontrolled edge, divided by

the time between PLL controlled edges, expressed as a percentage

VCC

VCC 2

GND

tP

T0

DC = tP/T0 x 100%

Figure 16. Cycle-to-Cycle Jitter

Figure 15. I/O Jitter

Figure 18. Output Transition Time Test Reference

tF

tR

VCC=3.3 V

2.4

0.55

TJIT() = |T0–T1mean|

CCLK0, 1

FB

The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample

of cycles

The variation in cycle time of a signal between adjacent cycles, over a random sample

of adjacent cycle pairs

TN

TJIT(CC) = |TN–TN+1|

TN+1

The deviation in cycle time of a signal with respect to the ideal period over a random

sample of cycles

TJIT(PER) = |TN–1/f0|

T0

Figure 17. Period Jitter

VCC=2.5 V

1.8

0.6