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ADF4002 Datasheet(PDF) 13 Page - Analog Devices

Part # ADF4002
Description  Phase Detector/Frequency Synthesizer
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4002 Datasheet(HTML) 13 Page - Analog Devices

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ADF4002
Rev. 0 | Page 13 of 24
FUNCTION LATCH MAP
PD2
PD1
MODE
0
X
X
1
X0
10
1
11
1
CPI6
CPI5
CP14
CPI3
CPI2
CPI1
3kΩ
5.1kΩ
11kΩ
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
TC4
TC3
TC2
TC1
0
0003
0
0017
0
01011
0
01115
0
10019
0
10123
0
11027
0
11131
1
00035
1
00139
1
01043
1
01147
1
10051
1
10155
1
11059
1
11163
F4
0
1
1
M3
M2
M1
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
F3
0
1
F2
0
1
F1
0
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
F1
PD1
M1
M2
M3
F3
P1
P2
CPI1
CPI2
CPI5
CPI6
TC4
PD2
F2
CPI3
CPI4
DB21
TC3
TC2
TC1
DB22
DB23
F4
F5
THREE-STATE
F5
X
0
1
NEGATIVE
POSITIVE
RESERVED
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
PHASE DETECTOR
POLARITY
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
FASTLOCK MODE
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
OUTPUT
TIMEOUT
(PFD CYCLES)
ICP (mA)
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
CE PIN
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
1.088
2.176
3.264
4.352
5.440
6.528
7.616
8.704
0.625
1.250
1.875
2.500
3.125
3.750
4.375
5.000
0.294
0.588
0.882
1.176
1.470
1.764
2.058
2.352
SEE PAGE 16
Figure 19. Function Latch Map



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