ADF4002

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

N Counter...................................................................................... 8

R Counter ...................................................................................... 8

Phase Frequency Detector (PFD) and Charge Pump.............. 8

MUXOUT and Lock Detect.........................................................9

Input Shift Register .......................................................................9

Latch Maps and Descriptions ....................................................... 10

Latch Summary........................................................................... 10

Reference Counter Latch Map.................................................. 11

N Counter Latch Map................................................................ 12

Function Latch Map................................................................... 13

Initialization Latch Map ............................................................ 14

The Function Latch.................................................................... 15

The Initialization Latch ............................................................. 16

Applications..................................................................................... 17

Very Low Jitter Encode Clock for High Speed Converters... 17

PFD............................................................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for Chip Scale Package .................... 18

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 21

REVISION HISTORY

4/06—Revision 0: Initial Version