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AND8020D Datasheet(PDF) 12 Page - Analog Devices

Part # AND8020D
Description  Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure
PDF  18 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
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AND8020D Datasheet(HTML) 12 Page - Analog Devices

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AND8020/D
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12
From this relationship,
DVA = DVO / 2, an incident wave
of half amplitude propagates down the transmission line. At
the Receivers input Point B, typically high impedance, the
transmission line sees an unterminated open line and the
signal reflection coefficient at the Receiver load is
approximately unity. The reflection causes the voltage to
double at the receiving end. When the reflected wave arrives
back at the source end, its energy is dissipated by the series
resistor. When the sum of the source and series impedance
is equal to the characteristic impedance of the line, no further
reflections occur.
Calculation of Rt
The Emitter Pull−Down Resistor, Rt, functions to
establish VOH and VOL levels. Voltage transitions imposed
on Rt propagate through RS and Z0 to a receiver. Negative
voltage transition are current limited by Rt, RS, and Z0 when
the driver output switches to the low state. The Rt value must
maximize the negative voltage transition and prevent the
output transistor from entering the cutoff operating region in
a low state (Figure 15).
*T−Line Z0
VEE
RS
Receiver
Figure 15. Equivalent Circuit for RE Determination
Driver
RO
Rt
The worst case scenario occurs when the driver output
emitter follower enters into cutoff during a negative going
transition. When this happens, the driver can be considered
opened and, at the instant it opens, the line characteristic
impedance behaves as a linear resistor returned to VOH. The
model becomes a simple series resistive network as shown
in Figure 16.
*T−Line Z0
VEE
RS
Figure 16. Equivalent Circuit with Output Cutoff
VEE
VOH
Rt
The maximum current, Imax, occurs at the instant the
switch opens and is calculated by:
I max +
(VOH * VEE )
(Rt ) RS ) Z0 )
(eq. 31)
An initial current, Iinit, must be sufficient to generate a
transient voltage equal to half of the logic swing since the
voltage at the receiver will double due the reflection
coefficient approaching 1.0 for series termination. To
accommodate reflections caused by discontinuities and load
capacitances the transient voltage should be increased by
25%. Thus, Iinit is defined as:
Iinit +
1.25 *
Vpp
2
Z0
(eq. 32)
To satisfy the initial constraints of Imax > Iinit:
( VOH * VEE )
( Rt ) RS ) Z0 )
u
1.25 *
VSWING
2
Z0
(eq. 33)
Solving for Rt, gives the inequality:
Rt v (KZ0 )Z0 * RS
(eq. 34)
Where:
Z0 = Line Characteristic Impedance
RO = Output Impedance of the Driver Gate
RS = Termination Resistance
KZ0 = Coefficient to Z0
For various series, the coefficient to Z0, KZ0, is presented
in Table E: Coefficient to Z0.
Table E. Coefficient to Z0
Series
KZ0
10EP
4.0
100LVEL
4.01
10EL
5.99
10E
7.10
100E
6.57
For the 10EP series (LVPECL mode operation),
where VOH = 2.4 V, VSWING = 0.8 V, and VEE = 0.0 V:
(2.4
* 0.0)
(Rt ) RS ) Z0)
y 0.5
Z0
*Z0 * RS y Rt
4.0
(eq. 35)
For the 100LVEL series (LVPECL mode operation),
where: VOH = 2.345 V, VSWING = 0.750 V, VEE = 0.0 V:
(2.345
* 0.0)
(Rt ) RS ) Z0)
y 0.468
Z0
*Z0 * RS y Rt
4.01
(eq. 36)
For the 10EL series (PECL mode operation),
where: VOH = 4.185 V, VSWING = 0.958 V, VEE = 0.0 V:
(4.185
* 0.0)
(Rt ) RS ) Z0)
y 0.599
Z0
*Z0 * RS y Rt
5.99
(eq. 37)



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